Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 22 Lecture 22: Multistage Amps Prof. Niknejad

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Lecture Outline Finish Current Mirrors An Example Using Cascodes Multistage Amps Cascode Amplifier: Magic!

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley The Integrated “Current Mirror” M 1 and M 2 have the same V GS If we neglect CLM (λ=0), then the drain currents are equal Since λ is small, the currents will nearly mirror one another even if V out is not equal to V GS1 We say that the current I REF is mirrored into i OUT Notice that the mirror works for small and large signals! High Res Low Resis

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Current Mirror as Current Source The output current of M 2 is only weakly dependent on v OUT due to high output resistance of FET M2 acts like a current source to the rest of the circuit

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Small-Signal Resistance of I-Source

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Improved Current Sources Goal: increase r oc Approach: look at amplifier output resistance results … to see topologies that boost resistance Looks like the output impedance of a common- source amplifier with source degeneration

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Effect of Source Degeneration Equivalent resistance loading gate is dominated by the diode resistance … assume this is a small impedance Output impedance is boosted by factor

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Cascode (or Stacked) Current Source Insight: V GS2 = constant AND V DS2 = constant Small-Signal Resistance r oc :

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Drawback of Cascode I-Source Minimum output voltage to keep both transistors in saturation:

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Current Sinks and Sources Sink: output current goes to ground Source: output current comes from voltage supply

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Current Mirrors Idea: we only need one reference current to set up all the currentsources and sinks needed for a multistage amplifier.

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Multistage Amplifiers Necessary to meet typical specifications for any of the 4 types We have 2 flavors (NMOS, PMOS) of CS, CG, and CD and the npn versions of CE, CB, and CC (for a BiCMOS process) What are the constraints? 1.Input/output resistance matching 1.DC coupling (no passive elements to block the signal)

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Summary of Cascaded Amplifiers General goals: 1.Boost the gain parameter (except for buffers) 2.Optimize the input and output resistances R in R out Voltage: Current: Transconductance: Transresistance:

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Start: Two-Stage Voltage Amplifier Use two-port models to explore whether the combination “works” CE 1 CE 2 Results of new 2-port: R in = R in1, R out = R out2 CE 1,2

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Add a Third Stage: CC Goal: reduce the output resistance (important spec. for a voltage amp) CE 1 CE 2 CC 3 Output resistance:

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Using CMOS Stages CS 1 CS 2 CD 3 Output resistance: Voltage gain (2-port parameter): Input resistance:

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Multistage Current Buffers Are two cascaded common-base stages better than one? Input resistance: R in = R in1

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Two-Port Models Output impedance of stage #1 (large)

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Common-Gate 2 nd Stage

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Second Design Issue: DC Coupling Constraint: large inductors and capacitors are not available Output of one stage is directly connected to the input of the next stage  must consider DC levels … why? 3.2V

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Alternative CG-CC Cascade Use a PMOS CD Stage: DC level shifts upward 3.2V

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley CG Cascade: DC Biasing Two stages can have different supply currents Extreme case: I BIAS2 = 0 A

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley CG Cascade: Sharing a Supply First stage has no current supply of its own  its output resistance is modified

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley The Cascode Configuration DC bias: Two-port model: first stage has no current supply of its own Common source / common gate cascade is one version of a cascode (all have shared supplies)

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Cascode Two-Port Model Output resistance of first stage = Why is the cascode such an important configuration?

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Miller Capacitance of Input Stage Find the Miller capacitance for C gd1 Input resistance to common-gate second stage is low  gain across C gd1 is small.

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Two-Port Model with Capacitors Miller capacitance:

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Generating Multiple DC Voltages Stack-up diode-connected MOSFETs or BJTs and run a reference current through them  pick off voltages from gates or bases as references

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Multistage Amplifier Design Examples Start with basic two-stage transconductance amplifier: Why do this combination?

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Two-Stage Amplifier Topology Direct DC connection: use NMOS then PMOS

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Current Supply Design Assume that the reference is a “sink” set by a resistor Must mirror the reference current and generate a sink for i SUP 2

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Use Basic Current Supplies

EECS 105 Fall 2003, Lecture 22Prof. A. Niknejad Department of EECS University of California, Berkeley Complete Amplifier Topology What’s missing? The device dimensions and the bias voltage and reference resistor