Design and Implementation of VLSI Systems (EN1600) Lecture 23: Sequential Circuit Design (2/2) Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

Sequencing methods

S. Reda EN160 SP’07 Sequencing timing terminology t pd Logic Prop. Delay t pdq Latch D-Q Prop Delay t cd Logic Cont. Delay t pcq Latch D-Q Cont. Delay t pcq Latch/Flop Clk-Q Prop Delay t setup Latch/Flop Setup Time t ccq Latch/Flop Clk-Q Cont. Delay t hold Latch/Flop Hold Time

1. Max-Delay (setup) constraint: Flip-flops

2. Max-Delay (setup) constraint: 2-phase latches

2. Min-delay (hold) constraint: Flip-flip

S. Reda EN160 SP’07 2. Min-delay (hold) constraint: 2-phase latches

S. Reda EN160 SP’07 3. Time borrowing

S. Reda EN160 SP’07 How much time can be borrowed? T borrow <= T c /2 –(t setup + t nonoverlap )

S. Reda EN160 SP’07 4. Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time –Decreases maximum propagation delay –Increases minimum contamination delay –Decreases time borrowing

S. Reda EN160 SP’07 4. Skew: flip-flops

S. Reda EN160 SP’07 4. Skew: 2-phase latches