Andrew Kahng – October Layout Planning of Mixed- Signal Integrated Circuits Chung-Kuan Cheng / Andrew B. Kahng UC San Diego CSE Department

Andrew Kahng – October 2001 Planning Resources Silicon Routing layers Elements Blocks Power/Ground Clocks Buses Goals Timing Power Feasibility

Andrew Kahng – October 2001 Mixed-Signal Planning Resources Silicon Routing layers Elements Blocks Power/Ground Clocks Buses Goals Timing Power Feasibility Unified and constrained: (1) polygon- and die-level optimizations; (2) device / interconnect embedding; (3) performance analysis and layout synthesis

Andrew Kahng – October 2001 Mixed-Signal Planning Scope Architecture Logic Layout System RF, Analog Digital Floorplan Geometry, Wires Feasibility, Performance

Andrew Kahng – October 2001 Initial Project Activities M/S Planning Capability M/S Context Circuit/System types Constraint types Figures of merit Design/layout best practices Use Model Layout Representation Devices, interconnects both first-class citizens System-level interconnect synthesis (e.g., arch / “cells”) Hybridization of topological, spatial representations Digital + A/MS Integration Power Isolation Technology (device and interconnect variability, heterogeneous integration) Constraint-Dominated Optimization Scalable, high-quality Focus on mixed-mode embedding, “primal-dual” opt Useful Background Interconnect synthesis (P/G, clock, signal topology) and RLC analysis (book,glossary) Multilevel optimizers since 1995: partitioning (MLPart), placement (Capo, CapoT) Primal-dual optimization frameworks Floorplan representations and optimizations: O-tree, corner block list, … + compaction Students, Faculty Bo Yao (PhD 2005), Mingyuan Li (PhD 2006) C.-K. Cheng, Andrew Kahng Understand Develop Leverage

Andrew Kahng – October 2001 Mixed-Mode Embedding Traditional blocks Traditional cells Mixed-Mode (blocks + cells) Mixed-Signal –RF, Analog, Digital Modules + Wires

Andrew Kahng – October 2001 Mixed-Mode: Blocks and Cells

Andrew Kahng – October 2001 Hierarchy Management/Reconciliation “Design Tree” “Layout Tree”

Andrew Kahng – October 2001 Traditional Context: Digital Control Datapath Control logic allowed to overlap because these are regions, not exact placements of hard cells. High regularity of datapath logic DP, repeaters, clock buffers, memory, BIST,…

Andrew Kahng – October 2001 “Classical Floorplanning Harmful” tutorial slide, ISPD April

Andrew Kahng – October 2001 Cell Placement (Commoditized) Based on: –Multi-level clustering (RTL hierarchy-aware, HEM, PinHEM, HEC, Rent-based, etc. etc. etc. variants) –Hybrid of analytic and partitioning methods –Bundled with incremental STA, basic timing/SI-driven opts Assume can leverage existing, foreseen technology –SPC, Cadence/Avant!/Mentor, Synopsys/Magma, … –Capo, CapoT, Dragon, Mongrel, Feng Shui (various LEF/DEF compatible open-source placers in MARCO GSRC Bookshelf)

Andrew Kahng – October 2001 Block Placement

Andrew Kahng – October 2001 O-Tree Representation Representation = key issue –Cover all kinds of floorplans –Easy to manipulate O-tree = good candidate –Covers both slicing and non-slicing –O(n) time to derive the floorplan –Handles various constraint types, e.g., symmetry –Tree structure  easy to represent interconnect channels –Current goal: Equal representation of both “modules” and interconnects

Andrew Kahng – October 2001 Power, ground, guard ring design Centering (thermal, process,…) Matching issues Area: manage relative impact Distance: match environment effects Shape, orientation: match process distortions Symmetry: differential signaling Constraints Parasitics: diffusion parasitic C, R; inductance (high-freq); interconnect coupling) Geometry: fixed locations, ARs/dimensions Isolation Substrate noise: distance, guard rings Thermal variation: distance from hot spots Power supply distribution Analog Layout Issues

Andrew Kahng – October 2001 RF Layout Issues Power/Ground EMI Main goal = performance RF design is wire-dominated Precise wire topology, length Planar layout Cf. Aktuna/Rutenbar 1999

Andrew Kahng – October 2001 Planning tools must understand sensitivities Buffer insertion, gate sizing, replication Wire sizing, shielding, signaling architecture Primal: Timing, routing completion, … Dual: Net cost, path cost, routing area cost, placement location cost, … Experience with e.g., provably good primal-dual approximations for multi-commodity flow (ICCAD00, ASPDAC01, ASPDAC02) Sensitivities and Primal-Dual Framework

Andrew Kahng – October 2001 SPARE SLIDES

Andrew Kahng – October 2001 Example Planning Issue: P/G Distribution

Andrew Kahng – October 2001 Example Planning Issue: Clock Distribution

Andrew Kahng – October 2001 Floorplan Representations Slicing Ordered Tree Sequence Pair Corner Block List Twin Binary Tree Ordered Tree

Andrew Kahng – October 2001 Slicing Floorplan A B C D E F A B C D E F Slicing Ordered Tree colors of adjacent nodes differ

Andrew Kahng – October 2001 A B C D E F C B A E D F X X X X F A D B C E Twin Binary Trees  (  1 )=11001  (  2 )=00110 order(  1 )=order(  2 )=ABCDFE

Andrew Kahng – October 2001 A B C D E F O-Tree SP1=(ABCDFE,FADEBC) SP2=(ABCDFE,FADBEC) CBL=(FADEBC,11101, ) CBL90=(ABCDFE,00110, ) B C A D F E

Andrew Kahng – October 2001 Relations Between Representations CBL (S,L,T) TBT (  +,  - ) O-tree T SP (s 1,s 2 ) 90 0 sequence tree transform