Rasit Onur Topaloglu University of California San Diego The ABOVE (Angle-Based On-Chip Variation Estimation) Technique for a Process Variation-Immune Design Dennis Lau National Semiconductor Hosam Haggag National Semiconductor

Process and on-chip variation model Motivation Validation methodology Outline Experimental Results Implementation Rasit Onur Topaloglu Conclusions Simulation Cost Reduction

Motivation Currently, the Synopsys static timing analysis tool, PrimeTime, neglects cell locations by default Process variations, if not considered properly, may cause chips to fail or prone designs to be impossible to attain a spec. Increases design time and reduces yield Logic path correlations are accounted for, but it is not satisfactory Cell locations contain a valuable systematic information Wafer sizes increasing, control in manufacturing progressing and feature sizes shrinking A simplistic process model is possible Rasit Onur Topaloglu

Oxide Distribution on Wafer Ref: Intel Technology Journal, Vol. 06, Issue 2, May cm wafer, 0.13  m, SEM Oxide distribution seems to be circular & continuous Rasit Onur Topaloglu

Process and OCV Models Rasit Onur Topaloglu

Modeling of Process Variations : “Volcano Model” Effects such as oxide variation, threshold voltage variation, lumped as cell speed variation Cell speed Distance from center Cell speed Equ-speed circles on wafer Increasing or decreasing cell speeds along radius Variation curves are circular Rasit Onur Topaloglu

Acquisition of the Volcano Model Design companies create their own test chips with different library blocks arranged in an oscillator or pulse time measurement device The test chips provides average cell speeds for each cell type on a particular region of wafer wherever the test chip is located Test chips are replicated over wafer A statistical analyses such as least squares fit can then be used to fit the model on data to identify the (DC) distribution center, following a normalization step to set cell speed at DC to 1 Rasit Onur Topaloglu

Second Order Extensions to the Model If test chips are small, a large number of them can be replicated over the wafer It becomes possible to identify more than one distribution center Elliptic contours may turn out to be more suitable Rasit Onur Topaloglu

The ABOVE Technique Particular location where a chip sits on wafer not known before fabrication The idea is to place a chip on particular locations on wafer and make sure that designing for these locations sufficient although the real chip might fall somewhere else on wafer The ABOVE technique is developed assuming Volcano model is valid; it can potentially be migrated to other process models Rasit Onur Topaloglu

Virtual Locations Simulated locations shall not necessarily correspond to actual locations allocated for chips on wafer Rasit Onur Topaloglu

Dominant Angles Simulated locations usually will be on different sides of the distribution center, hence these locations can be identified by an angle with respect to the DC (distribution center) The reason is that chips on these locations will have process variations effecting them from different directions  DC fast cells slow cells Notice how chips on different places have differing speed variations on them Rasit Onur Topaloglu

Linear Approximation of Process Variation Curves Cell speeds will be effected depending on angle wrt DC Assumption :  max. on-chip speed variation On-chip variation available as std. dev. only Since chips are small, circle arcs approximated to be straight lines model -real Process curves on chip chip1 chip2 DC Rasit Onur Topaloglu

Location of Chip Matters Equ-lines are taken to be parallel to each other and normal to the line that connects distribution center and closest corner of chip DC  Rasit Onur Topaloglu 0 deviation max deviation Each cell assigned a speed deration such that nearest and farthest cell has 0 and maximum deviations from nominal respectively

Calculation of Speed Variation   B A |A//B| / |B| ratio is used to find process variation effect at location p p Multiply this ratio by maximum on-chip variation to find cell speed Rasit Onur Topaloglu

Simulation Cost Reduction Rasit Onur Topaloglu

Hypothesis I : Chips on Same Angle It is satisfactory to check the location that covers more contours as compared to other locations on the same dominant angle In the example, location A&B on same dominant angle, but it is satisfactory to check B as it contains more contours lines A B Rasit Onur Topaloglu

Hypothesis II : Dominant Angles There exist a number of angles for which the timing check of a chip at virtual locations at these angles will satisfy the check of all remaining angles in between them In the example, 8 dominant locations checked, it is not necessary to check the location indicated by the purple box. Rasit Onur Topaloglu

Hypothesis III : Equivalence of Complementary Angles Checking for increasing process variation at an angle is equivalent to checking decreasing across-chip variation at its complementary angle In the example, checking for increasing process variations at location is equivalent to checking for decreasing process variations at locations Rasit Onur Topaloglu

Hypothesis IV : Passiveness of Common Variations Spatial variations are dominant in terms of resulting in worst case estimations as compared to common variations in all cells In the example, process contours are normalized with respect to 1.2, which is the common variation of the cell. Checking either cell is satisfactory Rasit Onur Topaloglu

Choice of Dominant Angles For a first order approximation, angles can be chosen as equally distributed In our experiments, we have used 8 angles separated by 45 o each An analytical solution needs to be implemented Rasit Onur Topaloglu

Extending ABOVE to include Second Order Modeling Effects For models with more than one DC, a chip can be affected by various directions A cross-over line is assumed for certain locations, number of simulations increase DC1 DC2 In the example, more locations would appear on the cross-over line Rasit Onur Topaloglu

Test and Validation of Proposed Methods Rasit Onur Topaloglu

Comparison with Probabilistic Cell Speeds Run script that changes cell speeds of a chip using a uniform distribution given max. on-chip variation Compare minimum setup times and hold times with a location based deterministic run Run script that changes cell speeds of a chip using a Gaussian distribution given max. on-chip variation For each dominant location angle { } Used to show that location based variations can be deteriorating as compared to probabilistic models due to systematic variation Rasit Onur Topaloglu

Proof I : Checking Validity of Method for Chips on Same Angle Run script that changes cell speeds of a chip at angle  Compare minimum setup times and hold times  runs For a number of variations up to max on-chip variation { } Used to show that for chips at same angle, simulating the chip that includes most contours is satisfactory Rasit Onur Topaloglu

Proof II : Checking Validity of Dominant Angles Run script that changes cell speeds of a chip given that angle Check that minimum setup or hold times are higher than found using dominant locations For a number of angles other than dominant angles { } Used to show that simulating for chips at dominant locations satisfactory for making sure that it will work on any location Rasit Onur Topaloglu

Proof III : Checking Validity of Complementary Angles Compare results of ABOVE with the complementary angle For each dominant angle { } Used to show that simulating for chips at complementary locations with differing magnitudes is equivalent Rasit Onur Topaloglu

Proof IV : Checking Validity of Common Variations Compare results and check if they give reasonably close results For a number of common variations { } Used to show that simulating for chips need not be done for various common variations Rasit Onur Topaloglu

Experimental Results Setup (max delay) Uniform random Gaussian random Location based Nominal Up to 20% variation in minimum slack observed on a microprocessor testcase Or, try setting clock to 1GHz whereas your chip can 800MHz on most locations on wafer when less variation used Hypothesis I supported Rasit Onur Topaloglu

Where Location Based Method fits in PrimeTime? Setup (max delay) Hold (min delay) WCTYPBCBC/WCOCV max delays  paths for setup max delays  paths max data min clock delays for setup Location based falls here, more realistic than both directions underestimate overest. Rasit Onur Topaloglu

A Qualitative Comparison with Pre-existing OCV Methods Rasit Onur Topaloglu PVT effects are considered as being lumped similarly Either a bounding-box or a pair-wise deration used while taking capture blocks are reference. [ Both approaches are local solutions with increased computation; ABOVE brings a global approach by taking DC’s as reference

Conclusions Location based variation fits on a more realistic scale as compared to built-in PrimeTime methods Probabilistic models fail to be satisfactory as they neglect deterministic systematic relationship between cells Dominant locations provide a means to reduce simulation time, yet integrate more accurate process variation effects Rasit Onur Topaloglu

Future Directions Incorporation of interconnect delay variations Proper selection of dominant locations A layout based mathematical approach Rasit Onur Topaloglu

Implementation Rasit Onur Topaloglu

Usage of Astro Output #this PERL script is used to input Astro data from the files cells.txt and locations.txt and output cellnloc.txt file that will be read by PrimeTime to update cell speeds. #!\bin\perl open (INFILE,"cells.txt"); open (IN2FILE,"locations.txt"); open (OUTFILE,">cellnloc.txt"); $line1= ; $file2length=$#lines2; $_=$line1; s/{//; /,$_); $maxcellno=$#cellnames; #shows one less than total in fact print "maxcellno=$maxcellno "; $found=1;#for reporting an assertation when cells are not found in locations.txt taken from Astro floorplan for ($i=0;$i<=$maxcellno;++$i) { foreach $line {$_=$line; if (/$cellnames[$i]/) { ($discard,$location)=split(/'/,$_); print OUTFILE "$cellnames[$i]'$location"; $found=0; last; } } if ($found) {print OUT2FILE "$cellnames[$i]";} $found=1;} Rasit Onur Topaloglu

Example of Output for Previous Step # The following is example entries in the text file cellnloc.txt acquired through previous script "U1"'( ) "U11"'( ) "U12"'( ) "U13"'( ) "U14"'( ) Rasit Onur Topaloglu

Creating PrimeTime Script #The following PERL script is used to use cellnloc.txt and create a PrimeTime script to be sourced by the main PrimeTime script to update cell speeds according to the ABOVE technique. #!\bin\perl open (INFILE,"cellnloc.txt"); #maximum on-chip variation of 20% is specified here $maxdiagder=0.2; #a dominant angle is specified here in radians $angle= ; #chip size specified here according to Astro output $wid=811.06; $len=808; #set to 0 for slow operating mode my $fast=0; #constant definitions my $pi=3.1415; my $piover2=$pi/2; my $piover4=$pi/4; open ; foreach $line1 #strip away left and right parentheses $line1=~ s/\(//; $line1=~s/\)//; $line1=~s/ /'/; $_=$line1; ($cname,$loc1,$loc2)=split(/'/,$_); Rasit Onur Topaloglu

Implementing Operations According to a Dominant Angle if ($angle <=atan2($len,$wid)){ $refx=$wid; $refy=$wid*sin($angle)/cos($angle); $hyporef=sqrt($refx*$refx+$refy*$refy); $hypoB=(($refy)*($len-$refy)/$hyporef)+$hyporef; $Bx=cos($angle)*$hypoB; $By=sin($angle)*$hypoB; } elsif ($angle <=$piover2){ $refx=$len*cos($angle)/sin($angle); $refy=$len; $hyporef=sqrt($refx*$refx+$refy*$refy); $hypoB=(($refx)*($wid-$refx)/$hyporef)+$hyporef; $Bx=cos($angle)*$hypoB; $By=sin($angle)*$hypoB; }. Rasit Onur Topaloglu

Implementation of Projection and Normalization #dot product of A and B $dotprod=($loc1*$Bx)+($loc2*$By); #x value for A projected on B $projx=$dotprod*$Bx/($hypoB*$hypoB); #y value for A projected on B $projy=$dotprod*$By/($hypoB*$hypoB); #length of A projected on B $line=sqrt ($projx*$projx+$projy*$projy); #length of reference line if ($fast==1){ $derval=1+($line/$hypoB)*$maxdiagder; } else { $derval=1-($line/$hypoB)*$maxdiagder; } print OUTFILE1 "set_timing_derate $derval $cname\n"; close INFILE; close OUTFILE1; Rasit Onur Topaloglu

Output of Previous Step # The following is example entries in the PrimeTime file derate_cell.pt created by the script above. set_timing_derate "U1" set_timing_derate "U11" set_timing_derate "U12" set_timing_derate "U13" set_timing_derate "U14" Rasit Onur Topaloglu