1 Scalable Pattern Matching for High Speed Networks Authors: Christopher R.Clark and David E. Schemmel Publisher: Proceedings of IEEE Symposium on Field- Programmable Custom Computing Machines(FCCM) Present: Kia-Tso Chang Date: November

Three designed method on FPGA 1. brute-force, 2. deterministic finite automata (DFA) 3. non-deterministic finite automata (NFA).

Distributed comparators and Character Decoder 3

Pattern-matching module using multi-character decoder 4

Four-character parallel NFA circuit for the pattern “abcde” 5

Upper bound of per matcher

Each FPGA logic element (LE) can implement up to a four-input logic gate and a flip-flop,

Upper bound of per matcher

Experiment result 10

Experiment result 11

Throughput and capacity trade- off summary 12

Throughput and capacity trade- off summary

Performance comparison with previous work