Lesson 1 Introduction – “Is there a limit ?” Transistors – “CMOS building blocks” Physics, Cross section and Layout Views.

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Lesson 1 Introduction – “Is there a limit ?” Transistors – “CMOS building blocks” Physics, Cross section and Layout Views

Is there a limit: Moore’s Law Intel co-founder Gordon Moore chuckled at those who, in decades past, predicted the imminent demise of Moore's Law. 1) This is the dictum that resulted from his observation in 1965 that transistor density doubles every 18 months, 2) This pattern has held true to this day. 3) Last year's semiconductor sales were 17 percent of all electronics sales and 0.7 percent of the gross world product 4) This percentage that has risen slowly but steadily for 40 years. 5) A generation from now, semiconductors will comprise 5.6 percent of the gross world product. 6) It'll be at least a human generation before Moore's Law begins to run out of gas at around the 9nm.

The traditional semiconductor chip is finally approaching some fundamental physical limits. 1) A gate oxide that is only three atoms thick 0.045um Intel) 2) Further innovation in insulating materials. 3) Moore's Law, does not apply to analog circuitry It might raise the dynamic range of A/Ds by 1.5 dB per year but the noise rises as chip area shrinks. 4) Escalating cost of a semiconductor fab plant, currently US$3 billion per fab Also doubling every three years. 5) Lithography. CMOS structure, Interconnection, Power 6) "Life after Moore" marked an end to the fascination with SoC integration, beginning of "dis-integration," : separate amplifier chips perform analog functions. 7) Moore's Law projects a 59 percent per year increase in transistor density, but processor packing is only on a 15 percent per year. Human ingenuity keeps shrinking the CMOS transistor, but with increasingly expensive manufacturing facilities. But

Silicon

Psub Ptype

Lesson 2 MOSFET I-V CHARECTARISTIC MOSFET IV Curves MOSFET Analog/Digital Models &Propagation Delay

Lumped Analysis I D =Q N /T tr V drift =-  n E y =-  n (V D -V S )/L T tr =L 2 /  n* V DS Q N =Q n *W*L=Cox*(V G - V T )*W*L I DS =  n * C ox * W/L*(V G -V T ) * V DS MOSFET I-V CHARECTARISTIC

MOFET IV Curves

Analog Model=> Max Bandwidth

2 Digital Model=> Max Working frequency.

Lesson 3 Passive Elements The CMOS inverter – “A masterpiece”

Passive Elements R=  *L / (t*W) R=R SQUARE *L / W C=  0 / d

“A masterpiece” Logic levels MOST – a simple switch The CMOS inverter: –DC operation –Dynamic operation –Propagation delay –Power consumption –Layout –Why is it better than others (Nmos,Bipolar)??

Paulo MoreiraInverter15 CMOS logic: “0” and “1” Logic circuits process Boolean variables Logic values are associated with voltage levels: –V IN > V IH  “1” –V IN < V IL  “0” Noise margin: –NM H =V OH -V IH –NM L =V IL -V OL

Paulo MoreiraInverter16 The MOST - a simple switch