1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

2 Outlines Administration Lab. Overall View FPGA Architecture Transistors Gates

3 Administration Web site: WebBoard:

4 Administration Instructor: CK Cheng, CSE2130, Teaching Assistants: Thomas Weng, Renshen Wang, Chengmo Yang, Mingjing Chen,

5 Administration Schedule Lecture: 2:00-2:50PM, W, Center 212. Discussion: 3:00-3:50PM, W, Center 212. Office hours: 10:30-11:30AM, TTh, CSE 2130.

6 Administration Textbook Digital Design and Computer Architecture, David Money Harris and Sarah L. Harris, published by Morgan Kaufmann, Hardware Altera DE1 Education Kit

Administration Labs (68%): computer simulations, board demonstration, report write-up. One report per group. 1. Combinational Circuit Designs 2. The Specification and Usage of Flip-Flops 3. Finite State Machines 4. System Design using Datapath and Control Subsystems Final (30%): 3:00-4:30PM F6/12 7

8 Behavior description C, System C, Verilog, VHDL Register Transfer Level Verilog, VHDL Netlist of Logic Physical Layout Logic Synthesis Placement, Routing Mask Fabrication FPGAs 1.Data Representation 2.Synthesis: Logic, Physical Layout 3.Analysis: Functional, Timing Verification Overall View of Labs

9 FPGAs (Field Programmable Gate Arrays) Switch Matrix Wiring Channels Programmable Logic Block Switches -SRAM based (Flash memory) -Antifuse Disadvantages: Penalty on area, density, speed Advantages: Flexibility, low startup costs, low risk, revisions without changing the hardware

10Copyright © 2007 Elsevier 1- Transistors: Silicon Transistors are built out of silicon, a semiconductor Pure silicon is a poor conductor (no free charges) Doped silicon is a good conductor (free charges) –n-type (free negative charges, electrons) –p-type (free positive charges, holes)

11Copyright © 2007 Elsevier 1- MOS Transistors Metal oxide silicon (MOS) transistors: –Polysilicon (used to be metal) gate –Oxide (silicon dioxide) insulator –Doped silicon

12Copyright © 2007 Elsevier 1- Transistors: nMOS Gate = 0, it is OFF (source and drain are disconnected) Gate = 1, it is ON (channel between source and drain) Source= 0 => Drain=0 Source=1 => Drain=0.8 (Poor one)

1- Copyright © 2007 Elsevier1- Transistors: pMOS pMOS transistor is just the opposite –ON when Gate = 0 Source =0 => Drain = 0.2 (Poor zero) Source =1 => Drain = 1 –OFF when Gate = 1

14Copyright © 2007 Elsevier 1- Transistor Function

15Copyright © 2007 Elsevier 1- Transistor Function nMOS transistors pass good 0’s, so connect source to GND pMOS transistors pass good 1’s, so connect source to V DD

1- Copyright © 2007 Elsevier1- CMOS Gates: NOT Gate AP1N1Y 0 1

1- Copyright © 2007 Elsevier1- CMOS Gates: NOT Gate AP1N1Y 0ONOFF1 1 ON0

1- Copyright © 2007 Elsevier1- CMOS Gates: NAND Gate ABP1P2N1N2Y

1- Copyright © 2007 Elsevier1- CMOS Gates: NAND Gate ABP1P2N1N2Y 00ON OFF 1 01ONOFF ON1 10OFFON OFF1 11 ON 0

20Copyright © 2007 Elsevier 1- CMOS Gate Structure

21Copyright © 2007 Elsevier 1- NOR Gate How do you build a three-input NOR gate?

22Copyright © 2007 Elsevier 1- NOR3 Gate Three-input NOR gate

23Copyright © 2007 Elsevier 1- Other CMOS Gates How do you build a two-input AND gate?

24Copyright © 2007 Elsevier 1- Other CMOS Gates Two-input AND gate

1- Copyright © 2007 Elsevier1- Transmission Gates nMOS pass 1’s poorly pMOS pass 0’s poorly Transmission gate is a better switch –passes both 0 and 1 well When EN = 1, the switch is ON: –EN = 0 and A is connected to B When EN = 0, the switch is OFF: –A is not connected to B

Copyright © 2007 Elsevier1- Noise Anything that degrades the signal –E.g., resistance, power supply noise, coupling to neighboring wires, etc. Example: a gate (driver) could output a 5 volt signal but, because of resistance in a long wire, the signal could arrive at the receiver with a degraded value, for example, 4.5 volts

Copyright © 2007 Elsevier1- The Static Discipline Given logically valid inputs, every circuit element must produce logically valid outputs Discipline ourselves to use limited ranges of voltages to represent discrete values

Copyright © 2007 Elsevier 1- Logic Levels

Copyright © 2007 Elsevier 1- Noise Margins NM H = V OH – V IH NM L = V IL – V OL

Copyright © 2007 Elsevier 1- DC Transfer Characteristics Ideal Buffer: Real Buffer: NM H = NM L = V DD /2 NM H, NM L < V DD /2

Copyright © 2007 Elsevier1- DC Transfer Characteristics

Copyright © 2007 Elsevier1- V DD Scaling Chips in the 1970’s and 1980’s were designed using V DD = 5 V As technology improved, V DD dropped –Avoid frying tiny transistors –Save power 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, … Be careful connecting chips with different supply voltages

Copyright © 2007 Elsevier1- Logic Family Examples Logic FamilyV DD V IL V IH V OL V OH TTL5 ( ) CMOS5 ( ) LVTTL3.3 ( ) LVCMOS3.3 ( )

Copyright © 2007 Elsevier 1- Power Consumption Power = Energy consumed per unit time Two types of power consumption: –Dynamic power consumption –Static power consumption

Copyright © 2007 Elsevier 1- Dynamic Power Consumption Power to charge transistor gate capacitances The energy required to charge a capacitance, C, to V DD is CV DD 2 If the circuit is running at frequency f, and all transistors switch (from 1 to 0 or vice versa) at that frequency, the capacitor is charged f/2 times per second (discharging from 1 to 0 is free). P dynamic = ½CV DD 2 f

Copyright © 2007 Elsevier 1- Static Power Consumption Power consumed when no gates are switching It is caused by the quiescent supply current, I DD, also called the leakage current Thus, the total static power consumption is: P static = I DD V DD

Copyright © 2007 Elsevier 1- Power Consumption Example Estimate the power consumption of a wireless handheld computer –V DD = 1.2 V –C = 20 nF –f = 1 GHz –I DD = 20 mA

Copyright © 2007 Elsevier 1- Power Consumption Example Estimate the power consumption of a wireless handheld computer –V DD = 1.2 V –C = 20 nF –f = 1 GHz –I DD = 20 mA P = ½CV DD 2 f + I DD V DD = ½(20 nF)(1.2 V) 2 (1 GHz) + (20 mA)(1.2 V) = 14.4 W