Project 2: Cadence Help Fall 2005 EE 141 Ke Lu. Design Phase Estimate delay using stage effort. Example: 8 bit ripple adder driving a final load of 16.

Slides:

Advertisements

Similar presentations

ECE 3130 – Digital Electronics and Design

Advertisements

EE 5323 Project 16 Bit Sklansky Adder Phase 2 Report

Programmable FIR Filter Design

ALU Organization Michael Vong Louis Young Rongli Zhu Dan.

1 Specifications Functionality: AND, OR, XOR, ADD Maximum propagation delay : 2ns Power budget: 30mW Area: 200 µm ×400µm Prepared by: Christie Ma, Manjul.

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 1 Digital Integrated Circuits A Design Perspective Arithmetic Circuits Jan M. Rabaey Anantha.

SP2006 CSE598A/EE597G CAD Tool Tutorial Spring 2006 CSE598A / EE597G Analog-Digital Mixed-Signal CMOS Chip Design.

Parking Pal Team M1: Anna Kochalko Chris Moody Hong Tuck Liew John Wu Project Manager: Kartik Murthy November 5, 2007 Your digital parking meter of the.

[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 29 Overall Project Objective : Dynamic Control.

1 4-bit Decimation Filter Rashmi Joshi Siu Kuen(Steve) Leung Cuong Trinh Advisor: Dr. David Parent December 5, 2005.

Viterbi Decoder: Presentation #10 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 10: 5 th April Final Design Corrections.

ECE – 329 Fall 2007 Lab Manual for Xilinx Example: Design and simulation of a Half Adder Instructor: Dr.Botros.

1 16 BIT KOGGE-STONE TREE ADDER Shayan Kazemkhani Nghia Do Jia Kang Yu Toan Luong Advisor: David Parent May 8 th 2006.

San Jose State University Department of Electrical Engineering Dec 5th, Fall 2005 EE 166 PROJECT Advisor: Prof. David Parent Group Members Radhika Arora,

UC Berkeley, Dept of EECS EE141, Fall 2005, Project 2 Speed-Area Optimized 8-Bit Adder Presentation Slides.

Group M3 Jacob Thomas Nick Marwaha Craig LeVan Darren Shultz Project Manager: Zachary Menegakis April 11, 2005 MILESTONE 12 Final LVS & Simulation DSP.

[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 27 Overall Project Objective : Dynamic Control.

Group M3 Nick Marwaha Craig LeVan Jacob Thomas Darren Shultz Project Manager: Zachary Menegakis April 4, 2005 MILESTONE 11 LVS & Simulation DSP 'Swiss.

1 DESIGN OF 4-BIT ALU Fairchild Semiconductor DM74LS181 Prashanth Kommuri Akram Khan Gopinath Akkinepally Advisor: Dr. David W. Parent 5 December 2005.

Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design.

4-bit ALU Yamei Li, Yuping Liang Hua Qu, James Hsu

1 4-Bit ALU Chun-Wai Lee Shiela Valenciano Advisor: Dr. David Parent 12/05/05.

S. Reda EN1600 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 24: Computer-Aided Design using Tanner Tools Prof. Sherief Reda Division.

Sprinkler Buddy Presentation #8: “Testing/Finalization of all Modules and Global Placement” 3/26/2007 Team M3 Kartik Murthy Panchalam Ramanujan Sasidhar.

1 Design of 4-bit ALU Swathi Dasoju Mahitha Venigalla Advisor: David W.Parent 6 th December 2004.

1 DESIGN OF 8-BIT ALU Vijigish Lella Harish Gogineni Bangar Raju Singaraju Advisor: Dr. David W. Parent 8 May 2006.

1 4 BIT Arithmetic Logic Unit (ALU) Branson Ngo Vincent Lam Mili Daftary Bhavin Khatri Advisor: Dave Parent DATE: 05/17/04.

4 Bit Arithmetic Logic Unit Presented by Ipsita Praharaj, Shalaka Ghawate Advisor: Dr. David Parent Date:05/11/04.

ESE 570 Final Project Due Wednesday, May 5, 2004, 4:30 pm.

1 8 Bit ALU EE 166 Design Project San Jose State University Roger Flores Brian Silva Chris Tran Harizo Yawary Advisor: Dr. Parent May 2006.

1 8 Bit ALU Rahul Vyas Gyanesh Chhipa Jaimin Shah Advisor: Dr. David W. Parent 05/08/2006.

[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Mon. Nov. 24 Overall Project Objective : Dynamic Control.

[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Nov. 11 Overall Project Objective : Dynamic Control.

Adders. Full-Adder The Binary Adder Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB.

Lec 17 : ADDERS ece407/507.

Cadence Tutorial -- Presented by Chaitanya Emmela VLSI Research Group CACS.

Guest Lecture by Ben Magstadt CprE 281: Digital Logic.

L-EDIT Tutorial EEL 4310.

Lecture bases on CADENCE Design Tools Tutorial

The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – 30 Lab 5: Layout.

ASIC Design Flow – An Overview Ing. Pullini Antonio

ECE122 – Digital Electronics & Design

Command Interpreter Window (CIW)

Tanner Tools Tutorial S-Edit v13.0 Tutorial.

The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – 30 Lab 3: Layout.

Synopsys Custom Designer Tutorial for a chip integration using the University of Utah Standard Cell Libraries In ON Semiconductor 0.5u C5 CMOS Version.

Synopsys Custom Designer Tutorial for a chip integration using the University of Utah Standard Cell Libraries In ON Semiconductor 0.5u C5 CMOS Version.

CADENCE CONFIDENTIAL 1CADENCE DESIGN SYSTEMS, INC. Cadence Front to Back End Adil Sarwar March 2004.

Lab. I 1. CADENCE를 이용한 Layout

Bandgap Current Reference source: FEI4_A_CREF FEI4 collaboration. November 29, Vladimir Gromov NIKHEF, Amsterdam, the Netherlands.

Objectives Understand the design environment and flow

UC Berkeley, Dept of EECS EE141, Fall 2005, Project 2 Speed/Area Optimized 8-bit Adder Design Name 1 Name 2 Delay(  s) ·Area(  m 2 ) = {your number}

Quartus II Schematic Design Tutorial Xiangrong Ma

Integrated VLSI Systems EEN4196 Title: 4-bit Parallel Full Adder.

Final Assembly  Your final project chip consists of a core and a pad ring  Core is the guts  Pad ring (or pad frame) connects the guts to the outside.

SJTU 2006 SPADE Manual Ma Diming

Design of 4-bit ALU.

L 05 29Jan021 EE Semiconductor Electronics Design Project Spring Lecture 05 Professor Ronald L. Carter

1 R/2R DAC w/ SPI interface for the IBM 130nm Process Larry Ruckman Physics April2010.

EE141 Project: 32x32 SRAM Abhinav Gupta, Glen Wong Optimization goals: Balance between area and performance Minimize area without sacrificing performance.

ECE122 – Digital Electronics & Design Tanner Tools Tutorial Ritu Bajpai September 4, 2008.

EE141 Arithmetic Circuits 1 Chapter 14 Arithmetic Circuits Rev /12/2003 Rev /05/2003.

Serpentine Channel Demonstration Documentation on the setup and simulation of a complete basic injector-separation channel model design.

Written by Whitney J. Wadlow

Digital Block Design & Layout Logic gate (3INPUT NAND GATE) 구자연.

1 EE 382M VLSI 1 EE 360R Computer-Aided Integrated Circuit Design Lab 1 Demo Fall 2011 Whitney J. Wadlow.

4 BIT Arithmetic Logic Unit (ALU)

Written by Whitney J. Wadlow

NCSU CDK Setup & Example

EE382M VLSI 1 LAB 1 DEMO FALL 2018.

Presentation transcript:

Project 2: Cadence Help Fall 2005 EE 141 Ke Lu

Design Phase Estimate delay using stage effort. Example: 8 bit ripple adder driving a final load of 16. Rough estimate of Area. Sum over the size times LE of every gate.

Schematics: Using Hierarchy

1. Transistor Level Remember to use nmos4 and pmos4. Make sure you have the right tech lib attached. 0.24u process. Connect input and output pins accordingly.

2. Creating Symbol from Schematic In Schematic view, click Design->Create Cell View->From Cell View. Don’t bother making the symbol shape pretty because Cadence will crash.

3. Putting the Blocks Together Use “i” to instantiate symbols to build more complicated schematics. Use “l” hot key to label wire names to simplify connecting the blocks together. Example, VDD and GND.

Extracting Netlist In Schematic view, open the analog environment window by clicking Tools-> Analog Environment. Go to Setup-> Environment and change the settings to hSpice and hierarchal. Next go to Setup-> Simulator/Directory/Host and change the Project Directory. Finally, click Simulation-> Netlist-> Create Final Cadence will put the netlist in CELLNAME/ hspiceS/extracted/netlist/hspiceFinal Fix the model file by adding “.lib g25.mod TT”, change TSMC25DN to NMOS, and edit the.OPTION statement.

LAYOUT Pitfalls –Doing LVS after laying out the entire adder. –Not running DRC often. –Not budgeting space for routing. Plan ahead to avoid these. Otherwise, Cadence will make life miserable.

How to Pass LVS Plan ahead before laying out. Do stick diagrams first. Do LVS “incrementally.” Example, mirror adder.

LVS, Extracting from Layout

Summary START EARLY. Cadence will hang as more and more people use the machines. Check Design often, run DRC often. Catch bugs early. Worst case tp*A = 6 uS * um^2. You must do better.