Fast and Area-Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts Charles Chiang, Synopsys Andrew B. Kahng, UC San Diego Subarna.

Slides:



Advertisements
Similar presentations
Porosity Aware Buffered Steiner Tree Construction C. Alpert G. Gandham S. Quay IBM Corp M. Hrkic Univ Illinois Chicago J. Hu Texas A&M Univ.
Advertisements

New Graph Bipartizations for Double-Exposure, Bright Field Alternating Phase-Shift Mask Layout Andrew B. Kahng (UCSD) Shailesh Vaya (UCLA) Alex Zelikovsky.
OCV-Aware Top-Level Clock Tree Optimization
Efficient Process-Hotspot Detection Using Range Pattern Matching in Routing Stage Hailong Yao 1 Subarna Sinha 2 Charles Chiang 2 Xianlong Hong 1 Yici Cai.
O(N 1.5 ) divide-and-conquer technique for Minimum Spanning Tree problem Step 1: Divide the graph into  N sub-graph by clustering. Step 2: Solve each.
Native-Conflict-Aware Wire Perturbation for Double Patterning Technology Szu-Yu Chen, Yao-Wen Chang ICCAD 2010.
Tutorial on Subwavelength Lithography DAC 99
Minimum Implant Area-Aware Gate Sizing and Placement
Label Placement and graph drawing Imo Lieberwerth.
Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng 1 Ion I. Mandoiu 2 Qinke Wang 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department, University.
FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model FastPlace: Efficient Analytical Placement.
GREMA: Graph Reduction Based Efficient Mask Assignment for Double Patterning Technology Yue Xu, Chris Chu Iowa State University Form ICCAD2009.
Ahmed Awad Atsushi Takahash Satoshi Tanakay Chikaaki Kodamay ICCAD’14
TPL-aware displacement-driven detailed placement refinement with coloring constraints Tao Lin and Chris Chu Iowa State University 1.
Dual Graph-Based Hot Spot Detection Andrew B. Kahng 1 Chul-Hong Park 2 Xu Xu 1 (1) Blaze DFM, Inc. (2) ECE, University of California at San Diego.
Automated Layout and Phase Assignment for Dark Field PSM Andrew B. Kahng, Huijuan Wang, Alex Zelikovsky UCLA Computer Science Department
Multi-Project Reticle Design & Wafer Dicing under Uncertain Demand Andrew B Kahng, UC San Diego Ion Mandoiu, University of Connecticut Xu Xu, UC San Diego.
: Grid graph :Draw two rays from each concave point Rays are divided into non-intersected ray-segments Conflict pair: two ray segments from the same point.
WaferReticle Project Yield-Driven Multi-Project Reticle Design and Wafer Dicing Andrew B. Kahng 1, Ion Mandoiu 2, Xu Xu 1, and Alex Z. Zelikovsky 3 1.
Reticle Floorplanning With Guaranteed Yield for Multi-Project Wafers Andrew B. Kahng ECE and CSE Dept. University of California San Diego Sherief Reda.
University of CreteCS4831 The use of Minimum Spanning Trees in microarray expression data Gkirtzou Ekaterini.
Yield- and Cost-Driven Fracturing for Variable Shaped-Beam Mask Writing Andrew B. Kahng CSE and ECE Departments, UCSD Xu Xu CSE Department, UCSD Alex Zelikovsky.
UCSD VLSI CAD Laboratory BACUS-2008 Revisiting the Layout Decomposition Problem for Double Patterning Lithography Andrew B. Kahng, Chul-Hong Park, Xu Xu,
1 UCSD VLSI CAD Laboratory ISQED-2009 Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization Kwangok Jeong, Andrew.
Toward Performance-Driven Reduction of the Cost of RET-Based Lithography Control Dennis Sylvester Jie Yang (Univ. of Michigan,
Design Bright-Field AAPSM Conflict Detection and Correction C. Chiang, Synopsys A. Kahng, UC San Diego S. Sinha, Synopsys X. Xu, UC San Diego A. Zelikovsky,
An Algebraic Multigrid Solver for Analytical Placement With Layout Based Clustering Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Bo Yao, Zhengyong Zhu.
New Graph Bipartizations for Double-Exposure, Bright Field Alternating Phase-Shift Mask Layout Andrew B. Kahng (UCSD) Shailesh Vaya (UCLA) Alex Zelikovsky.
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering Puneet Gupta 1 Andrew B. Kahng 1 Stefanus Mantik 2
Detailed Placement for Leakage Reduction Using Systematic Through-Pitch Variation Andrew B. Kahng †‡ Swamy Muddu ‡ Puneet Sharma ‡ CSE † and ECE ‡ Departments,
Topography-Aware OPC for Better DOF margin and CD control Puneet Gupta*, Andrew B. Kahng*†‡, Chul-Hong Park†, Kambiz Samadi†, and Xu Xu‡ * Blaze-DFM Inc.
Triple Patterning Aware Detailed Placement With Constrained Pattern Assignment Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D.F. Wong.
Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost W. Liu, T. Chien and T. Wang Department of CS, NTHU,
Optimally Minimizing Overlay Violation in Self-aligned Double Patterning Decomposition for Row-based Standard Cell Layout in Polynomial Time Z. Xiao, Y.
Hsiu-Yu Lai Ting-Chi Wang A TPL-Friendly Legalizer for Standard Cell Based Design SASIMI ‘15.
Subwavelength Optical Lithography: Challenges and Impact on Physical Design Part II: Problem Formulations and Tool Integration Andrew B. Kahng, UCLA CS.
Homework solution Problem 2. The number of odd degree vertices in a graph is even. (recom. book: G. Harary: Graph Theory) Solution: Let G=(V,E,w) S= 
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
Hongbo Zhang, Yuelin Du, Martin D.F. Wong, Yunfei Deng, Pawitter Mangat Synopsys Inc., USA Dept. of ECE, Univ. of Illinois at Urbana-Champaign GlobalFoundries.
-1- UC San Diego / VLSI CAD Laboratory A Global-Local Optimization Framework for Simultaneous Multi-Mode Multi-Corner Clock Skew Variation Reduction Kwangsoo.
Horizontal Benchmark Extension for Improved Assessment of Physical CAD Research Andrew B. Kahng, Hyein Lee and Jiajia Li UC San Diego VLSI CAD Laboratory.
K.Yuan, J.Yang and D.Pan ECE Dept. Univ. of Texas at Austin
Low-Power Gated Bus Synthesis for 3D IC via Rectilinear Shortest-Path Steiner Graph Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, and Shih-Hung Weng UC San.
UC San Diego / VLSI CAD Laboratory Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop Insertion Andrew B. Kahng, Ilgweon Kang and Siddhartha Nath.
Kwangsoo Han, Andrew B. Kahng, Hyein Lee and Lutong Wang
Kwangsoo Han‡, Andrew B. Kahng‡† and Hyein Lee‡
Closing the Smoothness and Uniformity Gap in Area Fill Synthesis Supported by Cadence Design Systems, Inc., NSF, the Packard Foundation, and State of Georgia’s.
Tao Lin Chris Chu TPL-Aware Displacement- driven Detailed Placement Refinement with Coloring Constraints ISPD ‘15.
Register Placement for High- Performance Circuits M. Chiang, T. Okamoto and T. Yoshimura Waseda University, Japan DATE 2009.
Pattern Sensitive Placement For Manufacturability Shiyan Hu, Jiang Hu Department of Electrical and Computer Engineering Texas A&M University College Station,
Dept. of Electrical and Computer Engineering The University of Texas at Austin E-Beam Lothography Stencil Planning and Optimization wit Overlapped Characters.
1 Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang National Taiwan.
Self-Aligned Double Patterning Decomposition for Overlay Minimization and Hot Spot Detection H. Zhang, Y. Du, M. D.F. Wong, R. Topaloglu Dept. of ECE,
An Efficient Linear Time Triple Patterning Solver Haitong Tian Hongbo Zhang Zigang Xiao Martin D.F. Wong ASP-DAC’15.
Yen-Ting Yu Iris Hui-Ru Jiang Yumin Zhang Charles Chiang DRC-Based Hotspot Detection Considering Edge Tolerance and Incomplete Specification ICCAD’14.
Chin-Hsiung Hsu, Yao-Wen Chang, and Sani Rechard Nassif From ICCAD09.
Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes Sorin Dobre +, Andrew B. Kahng * and Jiajia Li * * UC San Diego VLSI CAD.
High-Performance Global Routing with Fast Overflow Reduction Huang-Yu Chen, Chin-Hsiung Hsu, and Yao-Wen Chang National Taiwan University Taiwan.
Outline Motivation and Contributions Related Works ILP Formulation
-1- UC San Diego / VLSI CAD Laboratory Optimization of Overdrive Signoff Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li and Siddhartha Nath Tuck-Boon Chan,
NanoCAD Lab UCLA Effective Model-Based Mask Fracturing Heuristic Abde Ali Kagalwalla and Puneet Gupta NanoCAD Lab Department of Electrical Engineering,
The minimum cost flow problem. Solving the minimum cost flow problem.
Xiaoqing Xu1, Tetsuaki Matsunawa2
1 Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs Zhi-Wen Lin and Yao-Wen Chang National Taiwan University.
Prof. Yu-Chee Tseng Department of Computer Science
VLSI Physical Design Automation
The minimum cost flow problem
Minimum Spanning Tree Algorithms
Automated Layout and Phase Assignment for Dark Field PSM
Presentation transcript:

Fast and Area-Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts Charles Chiang, Synopsys Andrew B. Kahng, UC San Diego Subarna Sinha, Synopsys Xu Xu, UC San Diego

Outline Introduction of AAPSM AAPSM Conflict Detection AAPSM Conflict Correction Conclusions

AAPSM: Enabling Technology Alternating Aperture Phase Shift Mask (AAPSM): Phase-modulation at the mask level to increase resolution capabilities of optical lithography. Mask Wafer

AAPSM: Enabling Technology Alternating Aperture Phase Shift Mask (AAPSM): Phase-modulation at the mask level to increase resolution capabilities of optical lithography Mask 180 o phase-shifter Wafer

AAPSM: Enabling Technology Alternating Aperture Phase Shift Mask (AAPSM): Phase-modulation at the mask level to increase resolution capabilities of optical lithography. Mask 180 o phase-shifter Shifters Mask Wafer Feature 0.11  m Printed using a 0.35 um nominal process

AAPSM: Enabling Technology Benefits: - Smaller feature sizes. - Better optical resolution - Extend equipment life Alternating Aperture Phase Shift Mask (AAPSM): Phase-modulation at the mask level to increase resolution capabilities of optical lithography.

Outline Introduction AAPSM Conflict Detection AAPSM Conflict Correction Conclusions

Additional Layout Rules Feature Rule: Shifters of the same feature must have different phases Overlapping Rule: Overlapping shifters must have the same phase 0180 Feature Shifters Overlapping Shifters Conflict: A pair of shifters violate the rules after phase assignment Legal Layout: No conflicts

Conflict Detection Problem Formulation Conflict correction lead to increased area Given: A layout (a set of shifters) Conflict weights = area increase for correcting the conflict Assign: phases to shifters To minimize the total area increase of all conflicts ConflictArea increase after correction

AAPSM Conflict Detection Flow Layout Conflict Cycle Graph Construction

AAPSM Conflict Detection Flow Layout Conflict Cycle Graph Construction Graph Planarization

AAPSM Conflict Detection Flow Layout Conflict Cycle Graph Construction Graph Planarization Graph Legalization / Phase Assignment

AAPSM Conflict Detection Flow Layout Conflict Cycle Graph Construction Graph Planarization Graph Legalization / Phase Assignment Check Removed Edge During Planarization

AAPSM Conflict Detection Flow Layout Conflict Cycle Graph Construction Graph Planarization Graph Legalization / Phase Assignment Check Removed Edge During Planarization Set of AAPSM conflicts for correction

Review of Work in Conflict Detection Conflict Graph Construction  Feature Graph (Kahng et al. ASPDAC 2003)  Phase Conflict Graph (Chiang et al. DATE 2005)  Conflict Cycle Graph (Non-bipartite Formulation) Graph Legalization  Iterative Voronoi Graph (Kahng et al. BACUS 98)  T-join based bipartization for planar graph (Berman et al. TCAD 2000)  Spanning Tree-Based Algorithm (Kahng et al. ASPDAC 2003)  Modified T-join algorithm for non-bipartite graph

Conflict Cycle Graph Node represents a shifter Feature edge connects two nodes of the same feature  Nodes of the feature edge have different phases Overlap edge connects overlapping nodes  Nodes of the overlap edge have the same phase Edge weight = conflict weight Remove one edge = correct the corresponding conflict Overlap edge Feature edge

Conflict Cycle and Conflict Face Conflict cycle = cycle with odd # feature edges Legal cycle = cycle with even # feature edges Conflict Fact: Legal Layout No conflict cycles

Phase Conflict Graph (DATE 2005) 9 edges Conflict Cycle Graph (Proposed) 5 edges Comparison with Previous Graph After removing uncorrectable edges 2 edges Uncorrectable edges can be removed with non-bipartite formulation

Min-Weight Edge-Deletion Fact: A planar graph has no conflict cycle if  Remove even number of edges for legal faces  Remove odd number of edges for conflict faces Legal Face Conflict Face

Min-Weight Edge-Deletion Problem Formulation Given: A planar conflict cycle graph G(V,E) Find: a set of edges E’ to be deleted such that  For each legal face, the number of edges in E’ is even  For each conflict face, the number of edges in E’ is odd To minimize the total weight of edges in E’ Flow to optimally solve the problem Conflict cycle graph  Dual graph (T-join problem) Dual graph  Gadget graph (Perfect matching problem) From optimal matching solution  edges to be deleted

Conflict Cycle Graph  Dual Graph face node dual edge edge Conflict Graph Dual Graph Conflict face  Conflict node Legal face  Legal node 4

T-join Problem Formulation Given: A graph G D (V, E, T) (T is the set of all conflict nodes) Find: a set of edges E’ to be deleted such that  For each node v, the edge number in E’ is odd iff To minimize the total weight of edges in E’ Conflict Graph Dual Graph facenode dual edge edge

Dual Graph  Gadget Graph node gadget Dual Graph true node edge T-join problem  min-weight perfect matching Gadget Graph

Perfect Matching Delete edges 1 and 2 + Phase assignment

Experiments Setup Implement proposed algorithms in C Use 4X400M Ultra-Sparc II with 4G RAM Ten large industry testcases  90 nm designs  # features from 10,274 to 159,070

Conflict Detection Results 5.9x Faster Speedup Ten Test Cases

Conflict Detection Results # Conflicts Ten Test Cases 3.88% Reduction

Outline Introduction AAPSM Conflict Detection AAPSM Conflict Correction Conclusions

Mask-level Conflict Correction Modify shifters on mask.  Split shifter region whenever two shifters of opposite phase overlap. Pros: no design modification Cons:  Increases mask complexity, correction not always possible  Can negatively affect process latitude Split

Widen Feature Increase width of certain features to make them non-critical No shifters needed for widened feature Widen Pros: small change in layout Cons: performance degradation

Add Spacing Insert vertical or horizontal gaps between overlapping shifters of different phases. Spacing Pros: small performance penalty as width of gate features remains unchanged Cons: larger area increase  Our focus

Insert gap locally Introduce new conflict Local versus Global Spacing Insert gap across the whole layout Large area increase

PSM Conflict Correction Divide layout into rows Divide each row into cells Original Layout

PSM Conflict Correction Insert gap across the cell to remove conflicts Divide layout into rows Divide each row into cells Original Layout

PSM Conflict Correction Insert gap across the cell to remove conflicts Adjust cell distance to avoid new conflicts Divide layout into rows Divide each row into cells Adjust row distance Original Layout

PSM Conflict Correction Insert gap across the cell to remove conflicts Adjust cell distance to avoid new conflicts Divide layout into rows Divide each row into cells Adjust row distance Original Layout Modified Layout

Generalized Correction Scheme H VVV HHH H H Solve conflicts within each region From the bottom of the tree  Insert spacing along the slicing line to avoid the conflicts between features of different regions

Conflict Correction Results DesignAreaConflict%Area Increase newold >100

Outline Introduction AAPSM Conflict Detection AAPSM Conflict Correction Conclusions

Conclusion AAPSM Conflict Detection:  First non-bipartite graph based approach  5.9x runtime improvement  3.88% conflict reduction AAPSM Conflict Correction:  Hierarchical layout modification  Small area increase on the average ( 6.1% ) for large testcases Future Work:  Incorporate feature widening as an option  Timing-driven PSM conflict correction

Thank You!