March 25, 20011de Sousa-Agrawal/ITSW01 An Experimental Study of Tester Yield and Defect Coverage Jose T. de Sousa INESC/IST, Technical University of Lisbon 1000 Lisboa, Portugal Vishwani D. Agrawal Circuit and Systems Research Lab Agere Systems, Murray Hill, NJ USA IEEE International Test Synthesis Workshop, Santa Barbara, CA

March 25, 20012de Sousa-Agrawal/ITSW01 VLSI Chip Yield n A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. n A chip with no manufacturing defect is called a good chip. n Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. n Cost of a chip: Cost of fabricating and testing a wafer Yield x Number of chip sites on the wafer

March 25, 20013de Sousa-Agrawal/ITSW01 Clustered VLSI Defects Wafer Defects Faulty chips Good chips Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77

March 25, 20014de Sousa-Agrawal/ITSW01 Yield Parameters n Defect density (d ) = Average number of defects per unit of chip area n Chip area (A ) Clustering parameter (  ) n Negative binomial distribution of defects, p (x ) = Prob(number of defects on a chip = x )  (  +x ) (Ad /  ) x = x !  (  ) (1+Ad /  )  +x where  is the gamma function  =0, p (x ) is a delta function (max. clustering)  =, p (x ) is Poisson distr. (no clustering) 

March 25, 20015de Sousa-Agrawal/ITSW01 Yield Equation Y = Prob( zero defect on a chip ) = p (0) Y = ( 1 + Ad /  )  Example: Ad = 1.0,  = 0.5, Y = 0.58 Unclustered defects:  =, Y = e -- Ad Example: Ad = 1.0,  =, Y = 0.37 too pessimistic !  

March 25, 20016de Sousa-Agrawal/ITSW01 Defect Level or Reject Ratio n Defect level (DL) is the ratio of faulty chips among the chips that pass tests. n DL is measured as parts per million (ppm). n DL is a measure of the effectiveness of tests. n DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.

March 25, 20017de Sousa-Agrawal/ITSW01 Determination of DL n From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL. n From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL.

March 25, 20018de Sousa-Agrawal/ITSW01 Modified Yield Equation n Three parameters: n Fault density, f = average number of stuck-at faults per unit chip area Fault clustering parameter,  n Stuck-at fault coverage, T n The modified yield equation: Y (T ) = (1 + TAf /  ) -  Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips, Y = Y (1) = (1 + Af /  ) - 

March 25, 20019de Sousa-Agrawal/ITSW01 Defect Level Y (T ) - Y (1) DL (T ) = Y (T ) (  + TAf )  = (  + Af )  Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A,  is the fault clustering parameter. Af and  are determined by test data analysis.  , Y (T ) = e --TAf and DL(T) = 1 -- Y (1) 1--T

March 25, de Sousa-Agrawal/ITSW01 Example: SEMATECH Chip n Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont n 116,000 equivalent (2-input NAND) gates n 304-pin package, 249 I/O n Clock: 40MHz, some parts 50MHz 0.45  CMOS, 3.3V, 9.4mm x 8.8mm area n Full scan, 99.79% fault coverage n Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock n Data obtained courtesy of Phil Nigh (IBM)

March 25, de Sousa-Agrawal/ITSW01 Test Coverage from Fault Simulator Stuck-at fault coverage Vector number

March 25, de Sousa-Agrawal/ITSW01 Measured Chip Fallout Vector number Measured chip fallout

March 25, de Sousa-Agrawal/ITSW01 Model Fitting Clustered faults: Af = 2.1 and  = Measured chip fallout Y (1) = Chip fallout and computed 1-Y (T ) Stuck-at fault coverage, T Unclustered faults: Af = 0.31 Y (1) =

March 25, de Sousa-Agrawal/ITSW01 Computed Defect Level Defect level (ppm) Stuck-at fault coverage (%) Clustered faults  = Unclustered faults

March 25, de Sousa-Agrawal/ITSW01 Reexamine Assumption n Assumption: 100% fault coverage leads to zero defect level. n Reality: 100% defect coverage leads to zero defect level. n Must examine the two coverages.

March 25, de Sousa-Agrawal/ITSW01 Fault vs. Defect Coverage n Coverage = % of stuck- at faults detected by vectors. n Faults are countable. n Alternative definition: f(T) = Prob(detection by T vectors | a fault is present) n All faults assumed equally probable on a faulty chip. n Determined theoretically. n Coverage = % of real defects detected by vectors. n Many types, large numbers. n Alternative definition: d(T) = Prob(detection by T vectors | a defect is present) n Each defect may have a different probability of occurrence. n Determined experimentally. Fault coverage Defect coverage

March 25, de Sousa-Agrawal/ITSW01 Defect Coverage d (T ) = Prob (detection by T vectors|chip defective) Prob (failure by T vectors) = – Y (1) 1 – Y (T ) = – Y (1) Measured yield, Y (T ), and estimated true yield, Y (1), can provide a statistical estimate for defect coverage.

March 25, de Sousa-Agrawal/ITSW01 Defect and Fault Coverages Defect coverage d Fault coverage f Vector number Coverage

March 25, de Sousa-Agrawal/ITSW01 Defect vs. Fault Coverage Fault coverage, f Defect coverage, d d > f d< f

March 25, de Sousa-Agrawal/ITSW01 Conclusion n Defect coverage can be determined from the measured test data. n Assumption: Test must be capable of activating the defect, e.g., only data from at-speed test can determine the coverage of delay defects. n The assumption, “DL = 0 at f = 100%,” may be justified since fault coverage appears to be more pessimistic than defect coverage. n Any coverage is a transformation of test data: – Vector 0 = coverage 0 – Vector infinity = coverage 1 n Unclustered fault assumption adds pessimism.