Ring Counter Discussion 11.3 Example 32.

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Presentation transcript:

Ring Counter Discussion 11.3 Example 32

4-Bit Ring Counter

Note non-blocking assignment module ring4( input wire clk, input wire clr, output reg [3:0] q ); // 4-bit Ring Counter always @(posedge clk or posedge clr) begin if(clr == 1) q <= 1; else q[3] <= q[0]; q[2:0] <= q[3:1]; end endmodule Note non-blocking assignment

Aldec Active-HDL Simulation

Johnson Counter

johnson4.v module johnson4( input wire clk, input wire clr, output reg [3:0] q ); // 4-bit Johnson Counter always @(posedge clk or posedge clr) begin if(clr == 1) q <= 0; else q[3] <= ~q[0]; q[2:0] <= q[3:1]; end endmodule

Johnson Counter

A Random Number Generator

q3 q2 q1 q0 0 0 0 1 1 1 0 0 0 8 1 1 0 0 C 1 1 1 0 E 1 1 1 1 F 0 1 1 1 7 1 0 1 1 B 0 1 0 1 5 q3 q2 q1 q0 1 0 1 0 A 1 1 0 1 D 0 1 1 0 6 0 0 1 1 3 1 0 0 1 9 0 1 0 0 4 0 0 1 0 2 0 0 0 1 1

rand4.v module rand4( input wire clk, input wire clr, output reg [3:0] q ); // 4-bit Random number generator always @(posedge clk or posedge clr) begin if(clr == 1) q <= 1; else q[3] <= q[3] ^ q[0]; q[2:0] <= q[3:1]; end endmodule

A Random Number Generator

Clock Pulse clk inp Q2 Q0 Q1 outp

clk_pulse.v ); module clk_pulse( input wire clk; input wire clr; input wire inp; output wire outp; ); reg [2:0] Q; // clock pulse generator always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 0; else Q[2] <= inp; Q[1:0] <= Q[2:1]; end assign outp = Q[2] & Q[1] & ~Q[0]; endmodule clk_pulse.v

clk inp Q2 Q0 Q1 outp