Emulsion Scanning System “SUTS”

Follow Shot Optics

Non-stop tomographic image taking ( follow shot method ) Use Ultra High Speed Camera Max 100views/sec ～ 60cm 2 /h –Up to 3k frames per second.  Max 100views/sec ～ 60cm 2 /h Image taking by follow shot –No go-stop operation –No go-stop operation to avoid a mechanical bottleneck. –FOV displacement and Blur are canceled by moving lens

Real-time Image Filtering and Packing Processor Arrange readout segments to lines FIR filters Ring frame buffers Spatial filter and Pixel Packing LVDS Camera Interface LVDS Output Interface Camera In

Programmable Real Time FIR filter Ref. GC2011A 3.3V DIGITAL FILTER CHIP DATASHEET, GRAYCHIP, INC. Pixel Data Input Pixel Data Output Max. 31 taps ODD filter / 32 taps EVEN filter can be programmable. Programmable gain control can reduce the complexity of brightness control.

Processing speed : Up to 30cm 2 /h/board SUTS Track recognition board Internal Band width 21Gbyte/s/FPGA ×11

SUTS block diagram Camera Camera front end image processor Track recognition MASTER PC Slave PC Piezo driver Stage Piezo 1.3GB/s 6-10MB/s MB/s Lamp Slave PC

Scanning Efficiency Check Sample : double refreshed half size OPERA film exposed cosmic rays pl Cosmic ray 1.Pick up prediction tracks (pl1-pl2-pl4) 2.Search pl3 for basetrack (2sufaces) window : dx,dy < +-3micron dthx,dthy < +-70mrad Exist or not ID Scanning area B 10mm x 10mm Base Track Eff. Corresponds to sqrt of CSD eff.

window : dx,dy < +-3micron dthx,dthy < +-70mrad Angle displacement

Micro track angle resolution 16.2mrad16.1mrad16.3mrad17.0mrad Lens side 9.0mrad13.0mrad15.0mrad14.8mrad X proj  <0.1 X proj 0.1<  <0.2 X proj 0.2<  <0.3 X proj 0.3<  <0.4 Y proj  <0.1 Y proj 0.1<  <0.2 Y proj 0.2<  <0.3 Y proj 0.3<  <0.4

Micro track angle resolution 16.0mrad20.0mrad15.4mrad20.0mrad 10.0mrad13.0mrad15.3mrad12.8mrad Stage side X proj  <0.1 X proj 0.1<  <0.2 X proj 0.2<  <0.3 X proj 0.3<  <0.4 Y proj  <0.1 Y proj 0.1<  <0.2 Y proj 0.2<  <0.3 Y proj 0.3<  <0.4

Base Track angle resolution 3.2mrad3.6mrad3.7mrad4.4mrad 3.5mrad3.2mrad3.7mrad4.1mrad X proj  <0.1 X proj 0.1<  <0.2 X proj 0.2<  <0.3 X proj 0.3<  <0.4 Y proj  <0.1 Y proj 0.1<  <0.2 Y proj 0.2<  <0.3 Y proj 0.3<  <0.4

micron Base Track position resolution

micron

window : dx,dy < +-3micron dthx,dthy < +-70mrad Ph sum cut 0.0<=angle<0.1 : <=angle<0.2 : <=angle<0.3 : <=angle<0.4 : <=angle : 13 Base Track Efficiency 90% (=

Ph sum cut 0.0<=angle<0.1 : <=angle<0.2 : <=angle<0.3 : <=angle<0.4 : <=angle : 13 window : dx,dy < +-3micron dthx,dthy < +-100mrad Base Track Efficiency 90% (=

The 2 nd 2 /h (30views/sec)

The 2 nd 2 /h (60views/sec)

Conclusion and Prospects 2 S-UTS are ready. The 2 nd S-UTS achieved 40cm 2 /h of Speed by using ×50 Objective. Processing speed will be improved. –Camera occupancy is 2 /h,×50Objective. –New code for FPGA (×2 processing power is expected by double pipe-lines) will be available soon. Logic synthesize has been finished. Verifications are on going by simulator. –Increasing processing board is possible if necessary. There is possibility to enlarge FOV down to by using current objective and Piezo driver. More less magnification by using other optics. 5 SUTS processing boards are ready. Stage constructions are on going.

Schedule of SUTS setup Currently two SUTS is working in 20cm 2 /h. –2 nd stage already tested in 40cm 2 /h mode with 50x FOV lens. Number of SUTS will increase one / month. –March we will have 5 in total.

New Track Recognition Block Same Algorithm as UTS The target speed of track recognition is > 100cm 2 /h. –The limit by the camera and ×50 objective is 60cm 2 /h, but considering possibility to enlarge FOV. One of the most powerful FPGA* (but not very new, stable ) was used. *Virtex2 Pro 100 (1 – 5 max. /system),Virtex2 Pro 70 (10 – 50 max./system) 2VP70(SUTS) QL3060(UTS) Logic Cell 74,448 1,584 On-die Memory 5,904kbit N/A On-die CPU PPC405×2 N/A Max Frequency (16bitCNT) 348 MHz 97MHz Inter FPGA data transfer rate is up to 40Gbit/sec ⇔ 1.2Gbit/sec(UTS)

Ring Frame Buffer The max. 15 frames of delay time can be produced. After confirming the number of hit pixels, it can be decided to take image. Storing Images Read Images From Any Pos. Temporary Buffer

New Camera Output and Filtered Images Raw output (512×512pixels)Filtered by Image Pre-Processor

Perform zero suppression to the pixel data. –Reducing data size down to 1/16 Zero Suppress, Spatial filter and Packing

LVDS （ 3+1 ）  2 240Mbyte/sec (2.5 msec/view) 32bit Bi-directional FIFO Host interface SLAVE FPGAs Calculating Overlayed Image 0.125msec/view/angle/FPGA Power PC 405  2 Control and Clustering S-UTS Track Recognition Block diagram (revised) Block SRAM High band width and Fine Granularity 21.6GByte/sec or more ＰＰ Ｃ ＳＲＡ Ｍ ＰＰ Ｃ ＳＲＡ Ｍ ＰＰ Ｃ ＳＲＡ Ｍ ＰＰ Ｃ ＳＲＡ Ｍ ＰＰ Ｃ ＳＲＡ Ｍ Rocket IO  20 4Gbyte/sec From Camera Image-Pre-Processor Local Control BUS ＰＰ Ｃ ＳＲＡ Ｍ ＰＰ Ｃ ＳＲＡ Ｍ MASTER FPGA Reordering Packed Image Controlling Slaves

20cm 2 /h/board of scanning speed has been achieved. Very Wide Bus by using On-die Memory (built in FPGA). –8 way interleave memory access  8.0 –Dual port SRAM  2.0 –Main clock 120MHz  160MHz.  1.3 *(↓cost, slow speed grade ) –Two angle at the same time  2.0 *(↑logic optimization ) Memory Band Width = 21G Byte/sec/FPGA ⇔ 0.5G Byte/s/FPGA(UTS) The current logic cell occupancy is only ~37%. Twice performance can be achieved by computer work without any hardware modification.  No additional cost. System performance can be increased by adding more than one board. *compare to the previous presentation New Track Recognition Block (revised)

Ph distribution Stage side

Ph distribution Stage side