Mehdi Amirijoo1 Power estimation n General power dissipation in CMOS n High-level power estimation metrics n Power estimation of the HW part n Power estimation of the SW part n Simulations and results n Source: W. Fornaciari, P. Gubian, D. Sciuto, C. Silvano “Power Estimation of Embedded Systems….” IEEE Transactions on VLSI systems, V6, N2, 1998

Mehdi Amirijoo2 General power... n Estimating from system-level point of view. n Average power is related to the switching activity of the circuit nodes. n Power dissipation in CMOS devices is composed of a static and a dynamic part. Dynamic part is the most dominant. n C EFF is the effective switched capacitance.

Mehdi Amirijoo3 General power... n  i is the switching activity factor at node i. We assume spatial and temporal independence between nodes. n Also define the toggle rate as:

Mehdi Amirijoo4 High-level power estimation n The power dissipation in timing-constrained systems depends on the mode of computation: –Fixed throughput –Maximum throughput –Burst throughput –Metric for Fixed throughput: –Metric for Maximum throughput:

Mehdi Amirijoo5 High-level power estimation –Metric for Burst throughput: Systems with power shutdown techniques, ETR else M Burst n For an area-constrained system the following metric is efficient:

Mehdi Amirijoo6 Power Estimation of HW part n Analytical model based on VHDL description at behavioral/RT level and the probabilistic estimation of the internal switching activity. n Hierarchical estimation approach. n User supplied input probabilities rather than input patterns. n Assumptions: –The supply and ground voltage are fixed. –Synchronous sequential circuits. –Data transfer at register-register level. –ZDM

Mehdi Amirijoo7 Power Estimation of HW part n Inputs to the estimation: –The ASIC spec. –The allocation library, components implementing the macro-modules and the basic modules. –The technological parameters. –The switching activity of the I/O’s n The total average power dissipation is given by: –Average power dissipated by the I/O nets –Core internal nets

Mehdi Amirijoo8 Power Estimation of HW part –Data-path P DP, memory P MEM, control logic P CNTR, core processor P PROC n For estimating the P IO factor requires knowledge about switching activity (given by the spec) and the pad characteristics (capacitance etc). n P DP is divided into the following:

Mehdi Amirijoo9 Power Estimation of HW part n P MEM is proportional to: and We assume to have P i,m in the target library

Mehdi Amirijoo10 Power Estimation of HW part n P can be divided into: n Model the control unit as a probabilistic FSM - Markov chain. n The input signal probabilities (input switching activity factors) are obtained from the system-level specification. Also assume ZDM. n The average power dissipated by the kth input, depends on the switching activity factor  k and the input load capacitance C k

Mehdi Amirijoo11 n P x (C x ) is the average power consumption per MHz. Power Estimation of HW part n Let p ij = P(next = s j | present = s i ), conditional state transition probability. n Let P i be the steady state probability of the state s i (the probability to be in a certain state in an arbitrarily long sequence. Given the Markov chain we can solve this problem by solving the Chapman-Kolmogorov equations). n Let P ij = p ij P i be the total state transition probability.

Mehdi Amirijoo12 Power Estimation of HW part n TP, transition probability between two disjoint subsets –S = {s 1, s 2, …., s n } –S i and S j are disjoint subsets of S n Power dissipation of register (in general) can be divided into a switching and non-switching power.

Mehdi Amirijoo13 Power Estimation of HW part n Switching power P i relates to the toggle rate TR bi of the output of the register, while the P NSi relates to the power consumption during the clock edges. n P i (or TR bi )depends on the state switching activity and the state encoding. –b i is the ith bit of the state code (state bit).

Mehdi Amirijoo14 Power Estimation of HW part n Estimation of P COMB –Assume a gate X. –C i is the capacitance driven by the ith gate X. –P i (C i ) is the average power consumption per MHZ of the ith gate X. –TR i is toggle rate of the gate X (based on the probabilistic model of switching activity of X).

Mehdi Amirijoo15 Power Estimation of HW part n Moore-type FSM, –Power dissipation of P OUT is composed of a part related to the combinatorial net and a part related to the primary outputs driving the output capacitance. –The total state transition probabilities P ij between two states s i and s j are equal to the total transition probabilities between the corresponding outputs o i and o i

Mehdi Amirijoo16 Power Estimation of SW part n Bottom-up approach (TOSCA). –In TOSCA the specification is compiled in the VIS, by considering the average power consumption of each VIS instruction during the execution of a given program. Choosing VIS-level makes the analysis processor independent. n Estimate the power consumption of each block. n Estimate the total power consumption by weighing the power consumption of each block according to execution frequencies.

Mehdi Amirijoo17 Power Estimation of SW part n In general… n The average current or energy (V DD is fixed) of each instruction can be derived by: –Measurements or detailed information from the provider n However we have overheads in forms of pipeline stalls, cache misses etc. n The overheads have been measure to be less than 5% of the base energy per instruction. n Add the overheads to the base energy cost.

Mehdi Amirijoo18 Simulations and results n Background: –35 FSM’s from the MCNC-91 benchmark suite. –HCMOS6 tech, 0.35 um, 3.3 V, 100 MHz –FSM’s synthesized by Synopsys Design Compiler –Comparing to Sysnopsys Design Power (based on the synthesized gate-level netlist). n Average percentage error of 9.52% ( %)

Mehdi Amirijoo19 Simulations and results