April 16th, 2008 1 1 3 3 2 2 4 4 6 6 5 5 7 7 9 9 8 8 10 12 11 Photomask Japan 2008 Electrical Metrics for Lithographic Line-End Tapering Puneet Gupta 3,

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Presentation transcript:

April 16th, Photomask Japan 2008 Electrical Metrics for Lithographic Line-End Tapering Puneet Gupta 3, Kwangok Jeong 1, Andrew B. Kahng 1,2 and Chul-Hong Park 1 1 ECE UC San Diego, 2 CSE UC San Diego, 3 EE UC Los Angeles Motivation Electrical Impact of Line-End Ion / Ioff Modeling Procedure Main Objectives Ion / Ioff Model Model Accuracy Validation Misalignment Model Conclusion and Future Work New modeling framework for electrical impact of line-end shapes, considering misalignment errors. Model accuracy is within 0.47% and 1.28% for I on and I off, compared to 3-D TCAD simulation. Design rule implications of our model: analysis suggests that line-end design rules can be relaxed significantly in future nodes without affecting electrical characteristics of key (logic, SRAM) circuits. Our near-term goals: Provide a technology exploration framework that captures area and leakage tradeoffs of line-end parameters  designers’ rules of thumb, guidance for OPC engineers. Obtain electrically safe and lithographically robust, yet cost-effective and area-conserving, line-end design rules. Electrical simulation model  Silicon.  Taper shape under misalignment is a significant cause of this discrepancy Need for Formal Tapering Metrics Design rules have weak connections to geometric taper metrics, and can be expensive in terms of layout area.  Electrical properties of line-end shape must be considered in determining design rules. LEE vs. Capacitance Line-end extension increases C g because there exist fringe capacitance between line-end extension and channel. Capacitance vs. V th C g affects V th, following V th model equation. - C g increase  V th decrease - C g decrease  V th increase V th vs. Current I on and I off are functions of V th - V th increase  I on, I off decrease - V th decrease  I on, I off increase Increasing LEE LEE makes fringing fields to the channelC Taper affects V th of gate edge segments. + channel i i 0 i = Current without LEE effect Incremental current due to top LEE Incremental current due to bottom LEE top LEE bottom LEE Cut line Cross-section view … There exists misalignment error between gate and diffusion processes. Overlapping region (=actual channel) can be varied by misalignment error. Increase linewidth variation Sweep LEE length, measure I on and I off from both our model and TCAD simulator. Average magnitude of error: 0.47% for I on, 1.28% for I off Model (w/o misalignment) TCAD (DaVinci) Model (w/ misalignment) LEE (nm)Ion (uA)Ioff (pA)Ion (uA)Ioff (pA)Ion (uA)Ioff (pA) Traditional Line-End (Taper) Metrics - Line-end gap (LEG), line width at gate edge (LW0)  Have guided litho and RET for many years, but do not understand tradeoff of area, cost, and variation-robustness Our Main Objectives - Model electrical impact (I on and I off ) of line-end shape - Model linewidth variation accounting for misalignment - Verification of design rules considering:  Electrical impact of line-end shape  Manufacturing difficulty (OPC and Mask costs)  New design rules: Electrically safe, lithographically robust, cost-effective, and area-conserving Impact on SRAM Bitcell Capacitance Model Super-Ellipse Representation Super-Ellipse Representation for Tapering Until now: no framework or set of metrics to describe line-end shape. We propose super-ellipse as a first step in this direction. Typical Line-End Shapes According to the taper shape, the LEE design rule can be optimized to reduce the bitcell size. LW0 LEG Line-End Shortening (LES) Line-End Bridging (LEB) CgCg V th Misalignment has a probability, P(m). Linewidth Model Tapering and Bulge Necking Total Gate Cap. Line-End Cap. Current Distribution Along the Channel S DG Model of the Channel Segment (i on / i off ) BASE_CURRENT INCRE_CURRENT i on i off Whole Transistor Model (I on / I off ) Active Poly  r Impact of misalignment Rectangular-shaped LEE: negligible impact on I on and I off Tapering, bulge and necking: depending on the super-ellipse parameters, I off can increase substantially. SRAM Bitcell Layout vs. Line-End Design Rule (Line-End Length, Sharpness) vs. (Leakage, Area) Large n is better for leakage variation  it increases OPC and Mask costs. Impact on Standard Cell Standard Cell Layout vs. Line-End Design Rule (Line-End Length, Sharpness) vs. (Leakage, Area) Definition: A taper is the shape of a polysilicon line-end. Super-Ellipse Equation Model Details Which taper is best?