Coincidence Detector on SOPC Coincidence Detector on SOPC Spring Semester 2006 Midterm Presentation Presenting: Roee Bar & Gabi Klein Instructor:Ina Rivkin Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab

Sunday, June 18, 2006 Midterm Presentation Agenda Project Goals Project Goals Implementation Implementation Algorithm Algorithm Technical Details Technical Details Implementation Limitations Implementation Limitations Additional Technical Issues Additional Technical Issues Achieved So Far Achieved So Far Schedule Schedule

Sunday, June 18, 2006 Midterm Presentation Reminder In reality, the probability of the two events occurring exactly at the same time is practically zero. Therefore, we have to define a timeframe T. In reality, the probability of the two events occurring exactly at the same time is practically zero. Therefore, we have to define a timeframe T. Two events occurring in this timeframe, are called coincident events. Two events occurring in this timeframe, are called coincident events. T

Sunday, June 18, 2006 Midterm Presentation Goals Additional Goals: Create an event generator, which will be used to test the detector. Create an event generator, which will be used to test the detector. Thoroughly understand and document the features and capabilities of the Digital Clock Manager (DCM) on the Virtex II Pro. Thoroughly understand and document the features and capabilities of the Digital Clock Manager (DCM) on the Virtex II Pro. Main Goal: Detect two simultaneous events

Sunday, June 18, 2006 Midterm Presentation Implementation The detector and the generator will be implemented as a core on the Virtex II Pro platform, using the Xilinx XUPV2P Development Board. The detector and the generator will be implemented as a core on the Virtex II Pro platform, using the Xilinx XUPV2P Development Board. The core will detect coincidences of two events in a given timeframe and count them. The core will detect coincidences of two events in a given timeframe and count them.

Sunday, June 18, 2006 Midterm Presentation Algorithm Let’s examine a coincidence between two signals: Let’s examine a coincidence between two signals: A B A XOR B W Declare coincidence if T 1 <W<T 2. Declare coincidence if T 1 <W<T 2. Target: Find out if T 1 <W<T 2. Target: Find out if T 1 <W<T 2.

Sunday, June 18, 2006 Midterm Presentation Algorithm Let’s say W>T/2, where T is the clock cycle time. Let’s say W>T/2, where T is the clock cycle time. 1: 0<W<T 0: W T Under the premise that W>T/2, this circuit detects if W T/2, this circuit detects if W<T. SRFF A XOR B CLOCK’ CLOCK S Clk Q S Q SRFF * Synchronous SRFF F

Sunday, June 18, 2006 Midterm Presentation Algorithm We can improve resolution and detect T/N<W<2T/N. We can improve resolution and detect T/N<W<2T/N. Let’s take N phase shifted clocks where the k-th clock is shifted by kT/N Let’s take N phase shifted clocks where the k-th clock is shifted by kT/N Then, we’ll connect all the SRFF outputs to a counter. Then, we’ll connect all the SRFF outputs to a counter.

Sunday, June 18, 2006 Midterm Presentation Algorithm S Clk1 Q A XOR B S Clk2 Q S Clk3 Q S In1 In2 In3 InN Counts the Number of ‘1’ inputs S=1 S=2 S=3. S=k S=N =>. => 0<W<2T/N T/N<W<3T/N T/(2N)<W<4T/N. T/(K-1)<W<(K+1)T/N W>T With the result of S, we can determine the signal pulse width range. S ClkN Q

Sunday, June 18, 2006 Midterm Presentation Technical Details DCM maximum frequency – 450MHz, (Period: 2.3nSec) DCM maximum frequency – 450MHz, (Period: 2.3nSec) DCMs available for implementation – 4 DCMs available for implementation – 4 Each DCM has an output, and a 180° shifted output, which gives us total of 8 clocks. Each DCM has an output, and a 180° shifted output, which gives us total of 8 clocks. Minimal coincidence that can be detected: 0.56nSec (with slower clock frequency, 0.46nSec is also possible) Minimal coincidence that can be detected: 0.56nSec (with slower clock frequency, 0.46nSec is also possible)

Sunday, June 18, 2006 Midterm Presentation Implementation Limitations Forbidden: Signal A has a pulse, while Signal B is constant (or vice versa). Forbidden: Signal A has a pulse, while Signal B is constant (or vice versa). After each detection, there will be 3 clock cycles (~6.7nSec), in which, the detector will be unable to detect any coincidences (implementation restriction). After each detection, there will be 3 clock cycles (~6.7nSec), in which, the detector will be unable to detect any coincidences (implementation restriction).

Sunday, June 18, 2006 Midterm Presentation More Technical Issues How can we resolve metastability in the SRFF, due to the input signal? We can add another DFF before the SRFF, which will be used as a synchronizer to prevent metastability state. How can we resolve metastability in the SRFF, due to the input signal? We can add another DFF before the SRFF, which will be used as a synchronizer to prevent metastability state.

Sunday, June 18, 2006 Midterm Presentation Achieved so far Studied EDK & HDL Designer. Studied EDK & HDL Designer. DCM configuration and usage. DCM configuration and usage. Running sample applications on the Virtex2Pro processor. Running sample applications on the Virtex2Pro processor. Implemented Event Generator. Implemented Event Generator.

Sunday, June 18, 2006 Midterm Presentation Updated Schedule June-July – Detector implementation June-July – Detector implementation August – Converting project implementation to User IPs, and attaching to PLB. August – Converting project implementation to User IPs, and attaching to PLB. Till mid-September - Project verification and finalizing documentation. Till mid-September - Project verification and finalizing documentation.