Area-performance tradeoffs in sub-threshold SRAM designs

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Presentation transcript:

Area-performance tradeoffs in sub-threshold SRAM designs George Cramer Ping-Chen Huang

Motivation Consumer applications require low power and small memory design Implementing SRAM in subthreshold needs read/write assist circuits to maintain stability Area trades off with stability and power

Project Outlines Investigate the area-performance trade-offs of 3 subthreshold SRAM designs Four metrics: stability, delay, power, area Fixed stability as the only constraint Determine the most area-efficient subthreshold SRAM design as Vdd scales down

Subthreshold SRAM designs N. Verma and A. P. Chandrakasan, “A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy,” IEEE Journal of Solid-State Circuits, vol. 43, no. 1, Jan. 2008, pp. 141-149. B. H. Calhoun and A. P. Chandrakasan, "A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation," IEEE Journal of Solid-State Circuits, vol. 42, no. 3, Mar. 2007, pp. 680-688.

Modeling of SRAM Stability (a) Hold stress (b) Read stress (c) Write stress VQ low: M2 is off VQ low: M2 is off VQ low: M1 is off VQ high: M2 is off VQ high: M3 is off VQ high: VQB = 0

Modeling of SRAM Delay Hold margin case: -> SNMhold = -0.0347+0.5*VDD Read margin case: Write margin case:

Noise Margin Modeling Results Desired Read Margin = 80mV Desired Write Margin = 150mV

Modeling of Delay and Power EOP Assume α=1

SRAM Performance 6T design has smallest read delay for its smallest equivalent resistance from internal node to bitline 10T design has smallest EOP

Area-EOP Trade-off