9/29/05ELEC / Lecture 101 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Power Analysis: Logic Level Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

9/29/05ELEC / Lecture 102 Power Analysis Motivation: –Specification –Optimization –Reliability Applications –Design analysis and optimization –Physical design –Packaging –Test

9/29/05ELEC / Lecture 103 Abstraction, Complexity, Accuracy Abstraction levelComputing resourcesAnalysis accuracy AlgorithmLeastWorst Software and system Hardware behavior Register transfer Logic Circuit DeviceMostBest

9/29/05ELEC / Lecture 104 Spice Circuit/device level analysis Circuit modeled as network of transistors, capacitors, resistors and voltage/current sources. Node current equations using Kirchhoff’s current law. Average and instantaneous power computed from supply voltage and device current. Analysis is accurate but expensive Used to characterize parts of a larger circuit. Original references: L. W. Nagel and D. O. Pederson, “SPICE – Simulation Program With Integrated Circuit Emphasis,” Memo ERL-M382, EECS Dept., University of California, Berkeley, Apr L. W. Nagel, SPICE 2, A Computer program to Simulate Semiconductor Circuits, PhD Dissertation, University of California, Berkeley, May 1975.

9/29/05ELEC / Lecture 105 CaCa Logic Model of MOS Circuit CcCc CbCb V DD a b c pMOS FETs nMOS FETs C a, C b, C c and C d are node capacitances DcDc DaDa c a b D a and D b are interconnect or propagation delays D c is inertial delay of gate DbDb CdCd

9/29/05ELEC / Lecture 106 Spice Characterization Input data patternDelay (ps)Dynamic energy (pJ) a = b = 0 → a = 1, b = 0 → a = 0 → 1, b = a = b = 1 → a = 1, b = 1 → a = 1 → 0, b =

9/29/05ELEC / Lecture 107 Spice Characterization (Cont.) Input data patternStatic power (pW) a = b = a = 0, b = a = 1, b = a = b = 128.5

9/29/05ELEC / Lecture 108 Switch-Level Partitioning Circuit partitioned into channel-connected components for Spice characterization. Reference: R. E. Bryant, “A Switch-Level Model and Simulator for MOS Digital Systems,” IEEE Trans. Computers, vol. C-33, no. 2, pp , Feb G1G1 G2G2 G3G3 Internal switching nodes not seen by logic simulator

9/29/05ELEC / Lecture 109 Delay and Discrete-Event Simulation (NAND gate) b a c (CMOS) Time units 0 5 c (zero delay) c (unit delay) c (multiple delay) c (minmax delay) Inputs Logic simulation min =2, max =5 rise=5, fall=5 Transient region Unknown (X) X

9/29/05ELEC / Lecture 1010 Event-Driven Simulation (Example) a =1 b =1 c =1→0 d = 0 e =1 f =0 g =1 Time, t g t = Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 Activity list d, e f, g g Time stack

9/29/05ELEC / Lecture 1011 Time Wheel (Circular Stack) t= max Current time pointer Event link-list

9/29/05ELEC / Lecture 1012 Gate-Level Power Analysis Pre-simulation analysis: –Partition circuit into channel connected gate components. –Determine node capacitances from layout analysis (accurate) or from wire-load model (approximate). –Determine dynamic and static power from Spice for each gate. –Determine gate delays using Spice or Elmore delay analysis.

9/29/05ELEC / Lecture 1013 Elmore Delay Model W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp , Jan s R1 R2 R3 R4 R5 C1 C2 C3 C5 C4 Shared resistance: R45 = R1 + R3 R15 = R1 R34 = R1 + R3

9/29/05ELEC / Lecture 1014 Elmore Delay Formula N Delay at node k= 0.69Σ Cj × Rjk j=1 where N = number of capacitive nodes in the network Example: Delay at node 5= 0.69[R1 C1 + R1 C2 + (R1+R3)C3 + (R1+R3)C4 (R1+R3+R5)C5]

9/29/05ELEC / Lecture 1015 Gate-Level Power Analysis (Cont.) Run discrete-event (event-driven) logic simulation with a set of input vectors. Monitor the toggle count of each net and obtain capacitive power dissipation: P cap = Σ C k V 2 f all nodes k –Where: C k is the total node capacitance being switched, as determined by the simulator. V is the supply voltage. f is the clock frequency, i.e., the number of vectors applied per unit

9/29/05ELEC / Lecture 1016 Gate-Level Power Analysis (Cont.) Monitor dynamic energy events at the input of each gate and obtain internal switching power dissipation: P int = Σ Σ E(g,e) f(g,e) gates g events e –Where E(g,e) = energy of event e of gate g pre-computed from Spice. F(g,e) = occurrence frequency of the event e at gate g observed by logic simulation.

9/29/05ELEC / Lecture 1017 Gate-Level Power Analysis (Cont.) Monitor the static power dissipation state of each gate and obtain the static power dissipation: P stat = ΣΣ P(g,s) T(g,s)/ T gates g states s –Where P(g,s) = static power dissipation of gate g for state s, obtained from Spice. T(g,s) = duration of state s at gate g, obtained from logic simulation. T = vector period.

9/29/05ELEC / Lecture 1018 Gate-Level Power Analysis (Cont.) Sum up all three components of power: P = P stat + P int + P stat References: A. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc. International Workshop Low Power Design, J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan, “Simulation Algorithms, Power Estimation and Diagnostics in PowerMill,” Proc. PATMOS, C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, “The Design and Implementation of PowerMill,” Proc. International Symp. Low Power Design, 1995, pp