1 An Energy Efficiency Evaluation for Sensor Nodes with Multiple Processors, Radios and Sensors Deokwoo Jung Embedded Networks and Applications Lab (ENALAB) Yale University *Research sponsored by NSF

2 Challenges for designing energy efficient wireless sensor network Large set of Application domain  From a simple data logging to a complex signal processing Long sleep period  For surveillance application, typically more than 90 % of lifetime is in a sleep state Dynamic roles  A sensor node can perform various functionalities from a cluster head to a simple end node A large dynamic range of trade-off between power and performance The fundamental limit of electronics in single type of hardware

3 CPU Trend  Computation cost of 32bit-FFT and energy efficiency comparison in CPUs

4 Radio Trend Data transfer cost of and energy efficiency comparison in Radios

5 Energy Trade-off in different roles high-end CPU+ low-end radios low-end CPU+ high-end radios Large dynamic range of operation  Collect and Forward Processing and Report Computation Load Communication Load

6 Related work for energy optimization Energy-Efficient Platform  Telos [Berkley], ZN1[HITACHI], Stargate[Crossbow], mPlatform [MS], LEAP[UCLA], ASPIRE [Yale-UCLA-UMASS] Energy-Aware Wireless Communication  LEACH: Energy-efficient communication protocol for wireless sensor networks [Heinzelman00]  S-MAC: An Energy-Efficient MAC Protocol for Wireless Sensor Networks[Wei02]  A MAC protocol to reduce sensor network energy consumption using a wakeup radio.[Matthew05] Network-Wide Energy Optimization  SPAN: An energy-efficient coordination algorithm for topology maintenance in ad hoc wireless networks [chan01]  GAF: Geography-informed energy conservation for ad hoc routing, [Chu01]  STEM: Topology management for energy efficient sensor networks[Curt02] Cross-Layer Design and Optimization  Cross-layer design for lifetime maximization in interference-limited wireless sensor networks [Madan05]  Physical layer driven protocol and algorithm design for energy-efficient wireless sensor networks [Eugene01]

7 Our contribution Reconfigurable platforms - high & low-end components in one platform  A large dynamic range of energy and performance trade-off  Using the most efficient component subset for each task Its energy efficiency modeling has not been studied well  Energy efficiency gain given a hardware set?  Parameters of affecting energy efficiency?  Optimal operation points given workload? Inter – Component Communication Link Camera Motion Sensor PXA271TI MSP CC XS SensorCPURadio

8 Analytical Model of Evaluating Reconfigurable platform Main design consideration factors  Component Interconnect => Combination of each component  The choice of hardware => Lifetime bound Predicting energy behavior is a key step toward optimum reconfigurable platform design  Quantifying energy efficiency  Estimating energy efficiency gain  Identifying key parameters for energy efficiency

9 Reconfigurable sensor platforms Dual-Platform with Serial Interface  Straight-forward SERIAL design between high-end and low-end platform  Limited binding among system components  Lowest interconnect protocol overhead -> Lowest latency  Limited Bandwidth (< 3.4 Mbps at I 2 C in High Speed mode) Low-End Radio ( ) High-End Radio (802.11) Low-End CPU (TI MSP) Flash SDRAM Control High-End CPU (PXA271) Flash SDRAM Control CIF RIF MIF Low-End Sensor (Motion Sensor) High-End Sensor (Camera) IO MUX Real Time Clock Voltage Regulator

10 Reconfigurable sensor platforms Reconfigurable Platform with reconfigurable interconnect  Maximum Reconfigurability, Complexity, and Power  Smallest latency and highest throughput.  Maximum range of power mode -> Fine-grained power control Low-End Sensor (Motion Sensor) High-End Sensor (Camera) Real Time Clock Voltage Regulator Low-End Radio ( ) High-End Radio (802.11) Low-End CPU (TI MSP) Flash SDRAM High-End CPU (PXA271) MIF IO Flash SDRAM Reconfigurable Interconnect Inter Component Router Shared RAM and Arbiter RIF-1 RIF-2 MIF IO Component Power control

11 Architecture abstraction It ’ s all about path combination …

12 Model Sensor Operation as a Semi- Markov Decision Chain Trigger-Driven Energy Management Model  Power mode, time variable, and transition cost of current state are determined previous decision action A, e.g {l,h}={Low-end CPU, High-end radio }  Embedded chain in processing stage and communication stage characterizes workload profile in each stage. Pre- processing Stage S 0 Processing Stage S 1 Comm. Stage S 2 LHO Using Low-EndUsing High-EndOff

13 An Energy Efficiency Evaluation for Sensor Nodes with Multiple Processors, Radios and Sensors Closed form Energy Efficiency Formula Solving Bellman equation derived from semi Markov decision process Decision vectors of CPU and radios (Arrival rate, Proc.time in low-end CPU, Proc.time in high end CPU, Comm.time in low-end Radios, Comm.time in high end Radios, Function of Uk

14 An Energy Efficiency Evaluation for Sensor Nodes with Multiple Processors, Radios and Sensors Graphical Analysis Example of Energy Efficiency evaluation  simple low/high-end node and architecture with dynamic interconnect δ

15 An Energy Efficiency Model Verification Using LEAP node Architecture* (*) The low power energy aware processing (LEAP) embedded networked sensor system. In IPSN ’06

16 An Energy Efficiency Evaluation for Sensor Nodes with Multiple Processors, Radios and Sensors Simulation result – Optimal Average Power Consumption

17 An Energy Efficiency Evaluation for Sensor Nodes with Multiple Processors, Radios and Sensors Simulation result – Upper Bound of Energy Efficiency Gain

18 How much can we afford to spend on the interconnect ? Numerical result – Interconnect Chip Power Budget Dynamic Range of Power Mode in Platform δ=6.06 δ=5.06 >2x

19 Conclusion and Future work Follow the guideline before you build! Energy efficiency evaluation model of Reconfigurable platform  Framework to pursue a design flow for sensor platform with multiple sensors, CPUs, and radios.  Opportunity in designing an interconnect chip – Might improve its energy efficiency by 8 X  Design target for Interconnect chip: Power consumption bound, event arrival rate, dynamic range of power Reconfiguration algorithms and Simulation  Online estimation of system parameter  Optimal online reconfiguration algorithm  Simulation for proposed reconfiguration algorithms * For More information pleas, visit “ ”