Communication Between FPGA and LabView - FPGA part

Schematic of FPGA Program 2 Input Ports DAT/CMD ACLK ENA Output Ports Q ENAFB ACLKFB

Command Table 3 CMD(HEX)Subtrahend(H/B)Result(Binary)Meaning AA/ A9/ Checking Status of FPGA B9/ Active 300MHz CLK BB/ Active 150MHz CLK BC/ Active 100MHz CLK CD/ Active 60MHz CLK CF/ Active 30MHz CLK D0/ Active 10MHz CLK ??Start SEU Test ??Send Back Result ??Memory Test