Rajeev K. Ranjan Advanced Technology Group Synopsys Inc. On the Optimization Power of Retiming and Resynthesis Transformations Joint work with: Vigyan Singhal, Cadence Berkeley Labs, Berkeley Fabio Somenzi, Univ. of Colorado, Boulder Robert K. Brayton, Univ. of California, Berkeley

All circuit optimizations (T+S)* Re(T)iming (S)ynthesis Motivation Optimization capability of retiming and resynthesis - an open question Theoretical foundation for practical retiming and resynthesis based synthesis and verification

This Work C1 C2 (Retiming + Resynthesis) * (special 2-way split + merge) * Circuit G1 G2 State Graph

This Work (Retiming + Resynthesis) * G2 (special 2-way split + Merge) * C1 C2 Circuit G1 State Graph

Outline òBackground Complexity Result Extensions to retiming and resynthesis Summary

Background: Sequential Circuit Gates and memory elements Edge triggered Single global clock

Background: State Transition Graph (STG) States (values of latches) Transitions (input minterms) b a CIRCUIT: , STG:

Background: Combinational Synthesis Primary InputsPrimary Outputs Latch InputsLatch Outputs

Background: Retiming [Leiserson & Saxe] Retime by +1 Retime by -1

Iterative Retiming and Resynthesis: (T + S) * Retiming changes interaction between different combinational blocks Combinational synthesis generates new candidate latch locations Sequence of retiming and synthesis provides powerful sequential optimization technique  [Malik and Sentovich]  [Iyer and Ciesielski]  [Hassoun and Ebling]

Retiming & Resynthesis: Optimization Capability Previous Work [Malik91]: Fixed states and transitions:- arbitrary state encoding General STG transformations:- incomplete classification STG (states, transitions, encoding) transformation Our Work: General STG transformations:- Complete and tight classification

State Transformations: Split and Merge [Malik91] s v b u a c d s1 s2 v b b u a a c d SPLIT MERGE

Definition: 1-Step Equivalence of States Defined over a pair of states in an STG. s t v b b u a a s and t indistinguishable in 1 step p p

Definition: 1-Step Equivalent Transformation Defined as 2-way merge and split involving 1-step equivalent states

Definition: 1-Step Equivalent Graphs Class of graphs obtained by applying a sequence of 1-step equivalent transformations 1StepEquivalence Applied to sufficiently delayed configuration of circuits

Definitions: Summary States Given an STG, states with identical transitions. Transformations Merge twostates Split a state into twostates Given an STG, Graphs Given two STG’s transformations G1 G2

Outline Background òComplexity Result Extensions to retiming and resynthesis Summary

C1 (S+T)* C2 G1G2 Prove for single transformation (generalize by induction). Prove for 2-way split. 2-way merge follows:  C2 can generate C1 (reversible transformations).  “2-way merge” on G2 leads to G1. Strategy:  Generate internal points for new codes.  Move latches to these internal points.

Generate New State Codes Trivial mapping for all states except s For s, split state ( t or u ) can be obtained by current state ( s1 ) and input ( c ) Trivial mapping back to original codes s s4 b s3 a c,d s2 s1 c,d G1 t u s4 b b s3 a a s1 s2 c d c d 2-way split G2

Implementing State Split C1 IN C C’ Synthesis C1 IN C C’ Retiming Synthesis C1 IN : Code for C1 : Code for C2 C2 IN

C1 (S+T)* C2G1G2 Synthesis does not change STG Retiming = (Basic retiming) * Basic retiming results in 1-step equivalent graphs Composition: G1G2 G X G1G X G2 Result follows by induction

Retiming Across NAND Gate Graphs are 1-step equivalent , -0 10

Retiming Across Fanout Junction Graphs are 1-step equivalent. Ignore transient states

and Graph Composition G1G2 G X G1G X G2 SPLIT s G1 s1 s2 SPLIT G2 s,t G1 X G s1,t s2,t G2 X G

Applying Compositionality G C1 = G Cx X G Cx G C2 = G Cx’ X G Cx Retime across Primitive Element C2C1 X X’ G C1 G Cx G Cx’ G C2 Applies to general retiming (by induction)

C1 (S+T)* C2G1G2 Synthesis does not change STG Retiming = (Basic retiming) * Basic retiming results in 1-step equivalent graphs Composition: G1G2 G X G1G X G2 Basic retiming within a circuit results in 1-step equivalent graphs Applies to general retiming by induction

Outline Background Complexity Result òExtensions to retiming and resynthesis Summary

Analysis Retiming and resynthesis optimization involves only a local notion of state equivalence Covers only a subset of all valid STG transformations

Limitation of (S + T)* - 1st Example C1C C1 (S+T)* C2 [Zhou97]

Extending Synthesis: Eliminate Floating Latches C Re-encoding C2 Eliminate floating latch

Limitation of (S + T)* - 2nd Example x y e e C1 x y e C C1 (S+T)* C2 else ,

Extending Retiming: Retiming Enabled Latches e e x y e RETIME x y e e x y ee x y e

All circuit optimizations Summary Characterized wrt STG transformations (S+T)* Re(T)iming (S)ynthesis Obtain tight bounds for extended transformations