Transmitter for Quantum Encryption System Supervisor: Yossi Hipsh Performed by: Asaf Holzer Edward Shifman High Speed Digital Systems Laboratory Midterm.

Slides:



Advertisements
Similar presentations
Module 5 – Sequential Logic Design with VHDL
Advertisements

Counters Discussion D8.3.
Assignments The submission has to be by the end of this week Write your full name and the group number on the answer sheet.
State-machine structure (Mealy)
Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.
Digital Logic Chapter 5 Presented by Prof Tim Johnson
Sequential Circuits1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
Presentation Final Project name: Synchronization for Quantum Encryption System Project supervisor : Yossi Hipsh. Project performed by : Omer Mor, Oded.
Transmitter for Quantum Encryption System Supervisor: Yossi Hipsh Performed by: Asaf Holzer Edward Shifman High Speed Digital Systems Laboratory Final.
1 Pulse Generator High Speed Digital Systems Lab Semestrial project – Winter 2007/08 Final Presentation Instructor: Yossi Hipsh Students: Lior Shkolnitsky,
D0525 Project Receiver for Quantum Encryption System By: Dattner Yony & Sulkin Alex Supervisor: Yossi Hipsh High Speed Digital Systems Laboratory Spring.
Transmitter for Quantum Encryption System Supervisor: Yossi Hipsh Performed by: Asaf Holzer Edward Shifman High Speed Digital Systems Laboratory Final.
1 Project supervised by: Dr Michael Gandelsman Project performed by: Roman Paleria, Avi Yona 12/5/2003 Multi-channel Data Acquisition System Mid-Term Presentation.
המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology.
Pulse Generator High Speed Digital Systems Lab Winter 2007/08 Design Presentation (Midterm ) Instructor: Yossi Hipsh Students: Lior Shkolnitsky, Yevgeniy.
1 Cross ID Tag identification emulator Part A final presentation Performed by: Raanan Steinberg Yido Shalev Project instructor: Yossi Hipsh Technion –
D0525 Project Receiver for Quantum Encryption System By: Dattner Yony & Sulkin Alex Supervisor: Yossi Hipsh High Speed Digital Systems Laboratory Spring.
Pulse Generator High Speed Digital Systems Lab Winter 2007/08 Project definition Instructor: Yossi Hipsh Students: Lior Shkolnitsky, Yevgeniy Lobanov.
1 Cross ID Tag identification emulator Final presentation Performed by: Shuki Yasharzada Raanan Steinberg Yido Shalev Project instructor: Yossi Hipsh Technion.
ENGIN112 L27: Counters November 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 27 Counters.
Transmitter for Quantum Encryption System Supervisor: Yossi Hipsh Performed by: Asaf Holzer Edward Shifman High Speed Digital Systems Laboratory.
High Speed Digital Systems Lab Spring/Winter 2010 Part A final presentation Instructor: Rolf Hilgendorf Students: Elad Mor, Ilya Zavolsky Integration of.
LabVIEW Design of Digital Integrated Circuits FPGA IC Implantation.
Quantum encryption system - receiver.1 D0525 Project Receiver for Quantum Encryption System By: Dattner Yony & Sulkin Alex Supervisor: Yossi Hipsh& Eli.
Quantum Encryption System - Synchronization presentation Midterm Project name: Synchronization for Quantum Encryption System Project supervisor : Yossi.
CS370 Counters. Overview °Counter: A register that goes through a prescribed series of states °Counters are important components in computers. °Counters.
RF Phenomenon Midterm presentation Written by: Jamil Shehadeh Naseem Jamal Supervisor: Yossi Hipsh 25/6/2007.
ENGIN112 L25: State Reduction and Assignment October 31, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 25 State Reduction and Assignment.
SEQUENTIAL CIRCUITS USING TTL 74XX ICS
Asynchronous Counter © 2014 Project Lead The Way, Inc.Digital Electronics.
Asynchronous Counters with SSI Gates
Pulse-modulated Radar Display Processor on a Chip Talal Darwich Center for Advanced Computer Studies University of Louisiana at Lafayette.
Introduction to Digital Logic Design Appendix A of CO&A Dr. Farag
Eng. Mohammed Timraz Electronics & Communication Engineer University of Palestine Faculty of Engineering and Urban planning Software Engineering Department.
Learning Outcome By the end of this chapter, students are expected to understand a few elementary components in digital system Decoder Multiplexer Demultiplexer.
High Speed Digital Systems Lab Spring 2008 Students: Jenia Kuksin Alexander Milys Instructor: Yossi Hipsh Midterm Presentation Winter 2008/2009.
Electronics for PS and LHC transformers Grzegorz Kasprowicz Supervisor: David Belohrad AB-BDI-PI Technical student report.
High Speed Digital Systems laboratory Midterm Presentation Spring 2009 Cellular Signal Source Student : Hammad Abed Essam Masarwi Instructor: Yossi Hipsh.
Senior Project By: RICARDO V. GONZALEZ Advisor: V. B. PRASAD.
Some features of V1495 Shiuan-Hal,Shiu Everything in this document is not final decision!
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 17 Dr. Shi Dept. of Electrical and Computer Engineering.
A Front End and Readout System for PET Overview: –Requirements –Block Diagram –Details William W. Moses Lawrence Berkeley National Laboratory Department.
CHAPTER 8 - COUNTER -.
Anurag Dwivedi. Basic Block - Gates Gates -> Flip Flops.
Sequential logic circuits
Counters and registers Eng.Maha Alqubali. Registers Registers are groups of flip-flops, where each flip- flop is capable of storing one bit of information.
COMBINATIONAL AND SEQUENTIAL CIRCUITS Guided By: Prof. P. B. Swadas Prepared By: BIRLA VISHVAKARMA MAHAVDYALAYA.
Chapter 3 Boolean Algebra and Digital Logic T103: Computer architecture, logic and information processing.
A versatile FPGA based photon counter and correlator sudersan dhep meet’16.
OMEGA3 & COOP The New Pixel Detector of WA97
ECE 3130 Digital Electronics and Design
HIDDEN ACTIVE CELL PHONE DETECTOR
Summary Latch & Flip-Flop
REMOTE JAMMING DEVICE.
EI205 Lecture 8 Dianguang Ma Fall 2008.
Computer Organization
Asynchronous Counters with SSI Gates
More Devices: Control (Making Choices)
XILINX FPGAs Xilinx lunched first commercial FPGA XC2000 in 1985
FIGURE 5.1 Block diagram of sequential circuit
CS Chapter 3 (3A and ) – Part 4 of 5
CPE/EE 422/522 Advanced Logic Design L03
Chapter 6 -- Introduction to Sequential Devices
Multi-Pixel Photon Counter Readout Board
Asynchronous Counters with SSI Gates
Programmable Electrically Erasable Logic Devices (PEEL)
University of Maryland Baltimore County Department of Computer Science and Electrical Engineering   CMPE 212 Laboratory (Discussion 10) Hasib Hasan
14 Digital Systems.
Advanced Computer Architecture Lecture 1
Chapter 10 Introduction to VHDL
Presentation transcript:

Transmitter for Quantum Encryption System Supervisor: Yossi Hipsh Performed by: Asaf Holzer Edward Shifman High Speed Digital Systems Laboratory Midterm presentation Spring 2006

Project Objectives The transmitter module is part of a complex system, which purpose is to send a digital code, which will later be used as key for encrypting and decrypting information. Our goal is to produce an electrical pulse which is ~0.5ns wide and its magnitude is 4v. The purpose of this pulse is to activate the laser diode.

The Overall System Block Diagram Computer (Controller) TransmitterReciever Interfrometers, etc. Computer + Counter Synchronization

Original Plan Pulse trigger D.D.LTTL 2 ECL ECL Programmable Delay Chip 1:2 ECL Programmable Delay Chip Long fiber And Gate1:2 Bal_UN Gain P_QuantP_Sync monostable

Original Plan – continued… Pulse trigger D.D.LTTL 2 ECL ECL Programmable Delay Chip 1:2 ECL Programmable Delay Chip Long fiber And Gate1:2 Bal_UN Gain RefP_Stab monostable

The ECL Programmable Delay Chip SY100EP195V (by Micrel) : Has 10 control bits, so we can delay the pulse by 2-12ns. (Delay range = 2 10 x step_delay = 2 10 x 10ps = 10ns) Conclusion: We can manage without the TTL delay (and the long fiber delay).

In order to improve the module’s performance we decided to use ECL technology from the very beginning of the pulse module, so we put the TTL-ECL device at the beginning. We replaced the components so they will operate in 3.3 voltage level. Some more advances

Pulse trigger TTL 2 ECL ECL Prog. Delay Chip 1:2And Gate 1:4 Bal_UN Gain monostable ECL Prog. Delay Chip ECL Prog. Delay Chip … … … P_Quant P_Sync Ref Plan #2

The Monostable (ECL) Flip Flop S R Q D ECL Prog. Delay Chip 1 ECL Prog. Delay Chip 3 ECL Prog. Delay Chip 2 1:4 (ECL) Q CLK MC100EP31 MC100EP31 Characteristics:

The Monostable Timing Diagram Data CLK Reset Q tsts t clk-Q t R-Q Q 400ps130ps Min. Pulse width: 530ps t t t t

Final Plan Computer – LabView 1:4 (TTL) Mux TTL-ECL Pulse-Module 1:4 (TTL) sel counter P_QuantP_StabP_Sync stab_ensync_ctrltrig detector ref

Inputs & Outputs Voltage Source trig. P_StabP_Quant (0.5 nsec) P_SyncRef (1) Ref (2) stab_ensync_ctrl counter

Final Plan – Pulse Module monostable And Gate 1:2 Bal_UN Gain Plan B 3ns0.5ns 10ns ref

Flip Flop S R Q D ECL Prog. Delay Chip 2 ECL Prog. Delay Chip 1 1:4 (ECL) Q CLK Final Plan – Pulse Module Flip Flop S R Q D ECL Prog. Delay Chip 3 ECL Prog. Delay Chip 5 ECL Prog. Delay Chip 4 1:4 (ECL) Q CLK 3ns 0.5ns And Gate 0.5ns

Final Plan – Timing Delays Time Table: Delay 1: 6.0ns Delay 2: 3.0ns Delay 3: 3.0ns 3.0ns Delay 4: 3.84ns 3.5ns Delay 5: 3.5ns 6.35ns Plan APlan B

The Bal-UN IN OUT 68Ω 140Ω 150Ω 1nF 100nF + -

Component List ComponentDescriptionManufacturerQuantity NB3L553-D1:4 TTLON Semi2 NLASB3157-DF (*)Multiplexer TTLON Semi2 MC100EPT20-DTTTL-PECLON Semi3 NB6N14S-MN (*)1:4 PECLON Semi6 MC100EP195-FAECL Prog. DelayON Semi15 MC100EP31 -DT (*)Flip FlopON Semi6 MC100EP05-DTN/AND GateON Semi3 MC100EP11-DT1:2 PECLON Semi3 (Self-Built)Bal-UN(Self-Built)6 ZPUL-30PAmplifierMini Circuits6 (*) To be approved by the project supervisor

The Transmitter Block Diagram P_Quant FPGA Spartan III PulseModule 1 P_Stab PulseModule 2 P_Sync PulseModule 3 Bus1Bus2

Achieved so far: Finished final design including pulse module with improvements (discussed before) Components have been chosen (some still waiting to be approved by the supervisor). Currently working on Orcad scheme.

Yet to do Approving new design by supervisor, including components. Finishing Orcad scheme. Ordering components. Wiring-up the circuit. Writing VHDL for the FPGA. Testing the wired-up circuit.