Logic Synthesis n -Basic Concepts and Tools n Tao Lin n Ohio Universtiy n February 17, 1998.

Slides:



Advertisements
Similar presentations
Representing Boolean Functions for Symbolic Model Checking Supratik Chakraborty IIT Bombay.
Advertisements

BDDs & Theorem Proving Binary Decision Diagrams Dr. Eng. Amr T. Abdel-Hamid NETW 703 Winter 2012 Network Protocols Lectures are based on slides by: K.
Irredundant Cover After performing Expand, we have a prime cover without single cube containment now. We want to find a proper subset which is also a cover.
Glitches & Hazards.
EEE324 Digital Electronics Ian McCrumRoom 5B18, Lecture 5: Software for.
Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Sum of Products.
Universal logic design algorithm and its application to the synthesis of two-level switching circuits §H.-J.Mathony §IEEE Proceedings 1989.
MVI Function Review Input X is p -valued variable. Each Input can have Value in Set {0, 1, 2,..., p i-1 } literal over X corresponds to subset of values.
Binary Recursion Tree The recursive Shannon expansion corresponds to a binary recursion tree Example: Path (v) to node v corresponds to cube c(v) Example:
ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions.
Two-Level Logic Synthesis -- Heuristic Method (ESPRESSO)
Logic Synthesis 2 Outline –Two-Level Logic Optimization –ESPRESSO Goal –Understand two-level optimization –Understand ESPRESSO operation.
1 Consensus Definition Let w, x, y, z be cubes, and a be a variable such that w = ax and y = a’z w = ax and y = a’z Then the cube xz is called the consensus.
Spring 07, Feb 13 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Binary Decision Diagrams Vishwani D. Agrawal James.
Binary Decision Diagrams1 BINARY DECISION DIAGRAMS.
Espresso Speedup ee219b project Yujia Jin. Presentation Overview Unate reduction for SCCC (reduce) –weakly unate –strongly unate –results Single sweep.
1 Multi-Valued Logic Up to now…two-valued synthesis –Binary variables take only values {0, 1} Multi-Valued synthesis –Multi-valued variable X i can take.
Logic Synthesis Outline –Logic Synthesis Problem –Logic Specification –Two-Level Logic Optimization Goal –Understand logic synthesis problem –Understand.
Boolean Functions and their Representations
Multi-Valued Input Two-Valued Output Functions. Multi-Valued Input Slide 2 Example Automobile features 0123 X1X1 TransManAuto X2Doors234 X3ColourSilverRedBlackBlue.
ENEE 6441 On Quine-McCluskey Method > Goal: find a minimum SOP form > Why We Need to Find all PIs? f(w,x,y,z) = x’y’ +wxy+x’yz’+wy’z = x’y’+x’z’+wxy+wy’z.
1 Multi-Valued Logic Up to now…two-valued synthesis –Binary variables take only values {0, 1} Multi-Valued synthesis –Multi-valued variable X i can take.
ECE Synthesis & Verification - Lecture 9b 1 ECE 697B (667) Fall 2004 ECE 697B (667) Fall 2004 Synthesis and Verification of Digital Systems Boolean.
Boolean Matching in Logic Synthesis. Equivalence of Functions Equivalence of two functions defined under l Negation of input variables l Permutation of.
Irredundant Cover After performing Expand, we have a prime cover without single cube containment now. We want to find a proper subset which is also a cover.
1 Generalized Cofactor Definition 1 Let f, g be completely specified functions. The generalized cofactor of f with respect to g is the incompletely specified.
 2001 CiesielskiBDD Tutorial1 Decision Diagrams Maciej Ciesielski Electrical & Computer Engineering University of Massachusetts, Amherst, USA
Winter 2014 S. Areibi School of Engineering University of Guelph
Logic Synthesis Primer
ECE 667 Synthesis and Verification of Digital Systems
Simple Minimization Loop F = EXPAND(F,D); F = IRREDUNDANT(F,D); do { cost = F ; F = REDUCE(F,D); F = EXPAND(F,D); F = IRREDUNDANT(F,D); } while ( F < cost.
Cube Calculus.
Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Two-Level Minimization I.
1 Binary Recursion Tree The recursive Shannon expansion corresponds to a binary recursion tree Example: Path  (v) to node v corresponds to cube c  (v)
ECE Synthesis & Verification - Lecture 8 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Multi-level.
Tautology. Tautology Decision May be able to use unateness to simplify process Unate Function – one that has either the uncomplemented or complemented.
Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Two-Level Minimization II.
BOOLEAN FUNCTION PROPERTIES
Binary Decision Diagrams (BDDs)
Combinatorial Algorithms Unate Covering Binate Covering Graph Coloring Maximum Clique.
Chapter 3. Minimization of Switching Functions. Given a sw function f(x 1, x 2, …, x n ) and some cost criteria, find a representation of f which minimizes.
Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Multi-Valued Logic.
Heuristic Two-level Logic Optimization Giovanni De Micheli Integrated Systems Centre EPF Lausanne This presentation can be used for non-commercial purposes.
ICS 252 Introduction to Computer Design Lecture 9 Winter 2004 Eli Bozorgzadeh Computer Science Department-UCI.
Two Level and Multi level Minimization
Daniel Kroening and Ofer Strichman 1 Decision Procedures An Algorithmic Point of View BDDs.
State university of New York at New Paltz Electrical and Computer Engineering Department Logic Synthesis Optimization Lect15: Heuristic Two Level Logic.
1 Verification of FSM Equivalence Goal: Verify that two sequential circuit implementations always produce the same sequence of outputs given the same sequence.
ECE Synthesis & Verification - Lecture 3/4 1 ECE 697B (667) Fall 2004 ECE 697B (667) Fall 2004 Synthesis and Verification of Digital Systems Two-level.
BDDs1 Binary Tree Representation The recursive Shannon expansion corresponds to a binary tree Example: Each path from the root to a leaf corresponds to.
Boolean Functions 1 ECE 667 ECE 667 Synthesis and Verification of Digital Circuits Boolean Functions Basics Maciej Ciesielski Univ.
1 ECEN 4703 Switching and Finite Automata Theory Sunil P Khatri University of Colorado, Boulder Spring 2002 Modified from lecture notes of Robert K Brayton,
Binary Decision Diagrams Prof. Shobha Vasudevan ECE, UIUC ECE 462.
ICS 252 Introduction to Computer Design Lecture 8 Winter 2004 Eli Bozorgzadeh Computer Science Department-UCI.
IT 60101: Lecture #121 Foundation of Computing Systems Lecture 13 Trees: Part VIII.
Heuristic Minimization of Two-Level Logic
EE4271 VLSI Design Logic Synthesis EE 4271 VLSI Design.
ECE 667 Synthesis and Verification of Digital Systems
Binary Decision Diagrams
MVI Function Review Input X is p-valued variable. Each Input can have Value in Set {0, 1, 2, ..., pi-1} literal over X corresponds to subset of values.
SAT-based Methods for Scalable Synthesis and Verification
Formal Methods in software development
ECB2212-Digital Electronics
MVI Function Review Input X is p-valued variable. Each Input can have Value in Set {0, 1, 2, ..., pi-1} literal over X corresponds to subset of values.
Heuristic Minimization of Two Level Circuits
Formal Methods in software development
A logic function f in n inputs x1, x2, ...xn and
Heuristic Minimization of Two Level Circuits
Tautology Decision May be able to use unateness to simplify process
A logic function f in n inputs x1, x2, ...xn and
Presentation transcript:

Logic Synthesis n -Basic Concepts and Tools n Tao Lin n Ohio Universtiy n February 17, 1998

n Introductory to some basic concepts; n Espresso; n Brief description to the BDD (Binary Decision Diagram).

F oundation for: n combinational and sequential synthesis n testing n timing and false paths n formal verication n asynchronous synthesis n automata theory n optimal clocking schemes n hazard analysis n power estimation n general combinatorics.

if f 1 = B n, f is the tautology, i.e. f  1; if f 0 = B n, (f 1 =  ) f is not satisfiable; if f(x) = g(x) for all x  B n, then f and g are equivalent; x 1 ; x 2 ; … are variables; x 1 ; x 1 ; x 2 ; x 2 ; … are literals;

A cover is prime irredundant if all its cubes are prime (irredundant). A prime of f is essential (essential prime) if there is a min-term (essential vertex) in that prime but in no other prime.

Shannon (Boole) Cofactors

Binary Recursion Tree

Unate Functions and Unate Covers A function is unate in x i if it is either positive unate or negative unate in x i.

Unate covers F have many extraordinary properties:  If a cover F is minimal with respect to singlecube containment, all of its cubes are essential primes.  In this case F is the unique minimum cube repre- sentation of its logic function.  A unate cover represents the tautology iff it contains a cube with no literals, i.e. a single tautologous cube.

IRREDUNDANT

EXPAND

Main idea of EXPAND

REDUCE

Reduce is order dependent.

REDUCE Algorithm

Unate Algorithm for SCCC

LSTGASP

A Brief Description of BDD (Binary Decision Diagram)

Acknowledgement n Most of the materials used here were selected from EE219b course note of UC- Berkeley. The author of these notes is Mr. R.K.Brayton. n Many thanks to people who give me help on preparing this talk.