Sun’s UltraSparc processors Sparc Version 9 architecture

UltraSparc family of processors All based on SPARC - Scalable Processor ARChitecture –Designed by Sun –RISC type of ISA 64- bit systems Previous generations used in Sun workstations and servers Current generation designed use in Servers

The newest member of the family: UltraSparc T2 processor, a multi-core, multi-threading ‘system on a chip’ So new, the servers just went on sale this month.

The T2 uses OpenSPARC Architecture 2007 which is an expansion of SPARC V.9 SPARC -V.9 was created by the architecture committee of SPARC International, a consortium of computer makers –Mainly Sun, Fujitsu, Motorola, and Toshiba It’s a RISC type of processor architecture with a load-store ISA model The V.9 supports 64-bit data and addressing while maintaining 32 bit instruction size for backwards compatibility It also has the capability of hardware 64 bit integer multiply and divide Version 9 added 16 additional double precision floating point registers for a total of 32. These registers can also be addressable as 8 quad precision floating point registers By default, SPARC is big-endian but v.9 allows for little-endian addressing as well.

Registers Registers are 64-bit wide A total of 128 Registers Uses Register windowing so only 32 registers are visible at any one time The 8 global registers are always visible –g0 is reserved for the value 0, so only 7 usable global registers The other 24 visible registers, called the “register window” or the “register stack” are comprised of: –8 ‘in’ registers used for input –8 local registers –8 ‘out’ registers used for output When the window ‘shifts’ the 8 out register becomes the next stack’s 8 in register.

Instructions Instructions are all 32- bit long Three major instruction formats The first two bits indicate the format type The rest of the op code is embedded in the middle of the instruction Source: UltraSPARC Architecture 2007 * Draft D0.9.1, 01 Aug 2007

The most interesting aspect of SPARC V.9’s instruction format is the single bit designated ‘p’ within the branch instruction format That 1-bit field is for the prediction for whether or not a branch will be taken. If 9 out of 10 times the branch will be taken that bit is set to 1.

SPARCS V.9 has many more instructions than MIPS For instance, the 2007 architecture has 38 different branch instructions as compared to the 2 branch instructions of MIPS. –It has 16 Branch on Integer Condition Codes like ‘Branch on Greater or Equal’ –It also has those same 16 branch instructions but with the single bit predictor code –Using a slightly different format of instruction SPARCS has an additional 6 Branch on Integer Register with Prediction instructions for comparing a register with Zero. At first glance SPARCS only has 4 Add instructions –But all logical and arithmetic instructions have an single bit ‘i’ field that indicates if the instruction is taking a register or an immediate

And finally: A Bizarre Instruction POPC - Population Count. –Count the number of one bits in a register or within an immediate and stores the result in a destination register. Image courtesy of:

This presentation is thanks to: SPARC International for the SPARC V.9 manual OPENSPARC and Sun Microsystems for the current draft of UltraSPARC Architecture Wikipedia And the National Oceanic and Atmospheric Administration

TEAM SPARC! Jake Meredith Nina Pavlich Karen Sottile Brian Williams Tyson Giezlar