AR2FL July 22, 2004 Anton, Campion, Mitch

Remaining Issues / Status One AR3FL board was stuffed in April by Godwin has been examined carefully. All locations readout and behave well on the detector. G1:summary excerpts from Log Investigating the board with a new cable. Chip % occupancy 120/60 ohms - ok. 12k resistors that go to VCDS are present.  FIXED by inverting A-B lines on cable. Chip 21 - odd testpulse has an offset by 20 counts (both in tpscan and tphigh) Chip 23- channel 3 bad - low gain G2 : Chip 1 (1b) - channel 9 is low-gain; Chip 49, 50 wrong address Should be 33,34.

300KHz Noise Rates No TP G1 G2

300KHz On Module G1 G2

Clock Noise on Module G1 G2

G1:TPScan all Locations 10 test pulse cnts Test Pulse Even Channels Test Pulse Odd Channels

G2: TPScan: 10 test pulse cnts Test Pulse Even Channels Test Pulse Odd Channels

G1:AR2FL High Threshold Scan Odd ChannelsEven Channels ? On Bench

G1:AR2FL High Threshold Scan On Module Odd ChannelsEven Channels ?

G2:AR2FL High Threshold Scan On Module Odd ChannelsEven Channels

Temp and Voltage Tests G1 vdd=2.51 Chip Temp Vdd Vcc Vee G2 Temp Vdd Vcc Vee

Shaper Select 0,0

Shaper Select 1, 1

Low Threshold Scan all Locations Odd Shaper 00 vs 11 (on Detector) G1 G2

AR2FL G1 Test Pulses Shaper 00 Shaper 11

AR2FL G2 Test Pulses Shaper 00 Shaper 11