APPLIED SIGNAL PROCESSING AND IMPLEMENTATION Introduction to 9 & 10th semester Fall 2005

2 ASPI Introduction Outline 1.Basic ASPI Model (A 3 ) 2.Trends from S8 -> S9 -> S10 3.Course overview 4.Project work 5.Reading suggestions 6.Formation of project groups 7.Group Rooms, Schedule, Home Page etc

3 ASPI Introduction A 3 Paradigm Application: Non-Linear Signal Processing etc. 1.Algorithm selection 2.Simulation 3.Architecture selection and modelling 4.Design Space Exploration 5.HW/SW Co-Design Applications Algorithms Architectures

4 ASPI Introduction Basic ASPI Model (A 3 ) Applications Algorithms Architectures For each application => many candidate algorithms For each algorithm => many implementation architectures => Large no. of solutions => Large Design Space

5 ASPI Introduction Focus of S8ASPI Applications Algorithms Architectures 1.Application to Algorithm Transformation 2.Simulation & Implementation Environments 1 2 3

6 ASPI Introduction Focus of S9 ASPI Applications Algorithms Architectures 1.App -> Alg:Non-Linear Signal Processsing and others 2.Simulation 4-5.Alg  Arch:HW/SW Codesign and Architecture Exploration

7 ASPI Introduction Focus of S10 ASPI Applications Algorithms Architectures 1.Proving your potential for R&D 2.Closing the loop

8 ASPI Introduction 9th Semester Applied Signal Processing and Implementation THEME: Non-linear DSP Methods and Real-Time Architectures PERIOD: 1 September – 31 January PURPOSE: To enable the students to understand, analyze, and employ state-of-the- art DSP methods and algorithms, for example in the domain of non-linear techniques. To enable the students to apply theories and methods to select, analyze and evaluate heterogeneous DSP- processor architectures given a DSP functionality under the constraint of some cost function.

9 ASPI Introduction Putting it all together SW Platform analysisHW Platform analysis SW compilersHW compilers Design Methodology Algorithm analysis Design Space Expoloration 8.sem9.Sem

10 ASPI Introduction 9th Semester Courses S9 Theme: Non-linear DSP Methods and Real-time Architectures FP9-2Discrete-Time Kalman Filtering2 ECTSSE/KB ASPI9-2A ASPI9-2B ASPI9-3 ASPI9-4 Mob9-2 HW/SW CoDesign HW Platform Analysis, Comp. & Optim. Non-linear Signal Processing Neural Networks Radio Communication III 2 ECTS 1 ECTS 1.4 ECTS PE/YM/PK PE/PR EL/UH EL/FF Project22 ECTS S10 Master Thesis in Applied Signal Processing and Implementation 30 ECTS EL : ELective Course

11 ASPI Introduction Project Work Overview Project Development Model 1.Application domain study 2.Algorithm Development and Simulation 3.Design Space Exploration 4.Implementation 5.Evaluation of results 6.Next step

12 ASPI Introduction Project Work Overview Project Development Model 1.Application domain study 2.Algorithm Development and Simulation 3.Design Space Exploration 4.Implementation 5.Evaluation of results 6.Next step

13 ASPI Introduction HW/SW Co-Design: generic flow

14 ASPI Introduction Project Work Technology Platform:Components:Lang.:Property: PC FPGA Pentium Proc. Sync. Logic PE’s Soft Proc. Hard Proc. C HandelC C Seq, Gips, 100 W Par, ??, ?? Seq, Mips, ?? FPGA Supplier: Components:Lang.:Property: Xilinx Altera Xilinx, Altera MicroBlaze Proc. PowerPC NIOS ARM Sync. Logic PE’s C HandelC 32 bit RISC 16 bit RISC 16/32 bit RISC ”Anything”

15 ASPI Introduction Project Work Content 2 conventional processor platforms 2 languages Complex Design Software => Keep projects simple(at first) Generic project example: Design, implement and test a processor/coprocessor architecture, that speeds up the execution of a selected algorithm or eventually a family or a set of algorithms

16 ASPI Introduction Project Work Content An example can be found in: Accelerating C Software Applications Results: iterations) FPGA, 50MHz w/o I/O X FPGA, 50MHz with I/O X Pentium, 3.6GHz X PPC405, 400MHz n/a 1 Iterations Notes: Figure 5. Test results for a range of maximum iteration values demonstrate substantial speedup of the algorithm (167X when using two parallel processes) compared to an embedded processor implementation.

17 ASPI Introduction Project Work Content Specific project examples: 1.Vector Co-processor (next pages) 2.Active Noise Cancellation in Headsets, Per Rubak 3.Any suitable algorithm, that you/we may suggest 1.GSM Vocoder (Ch. 5 in SpecC book) 2.H263 Video Decoder (prev. S10 project) 3.RS codec for DVB-H (prev. S10 project) 4.Digital Camera example (Ch. 7 in Vahid’s book) 5.Video filtering 6.3GDSP algorithm examples 7.A.s.o.

18 ASPI Introduction Vector Inner Product (1) c = a T b (a transposed times b) c is a scalar, a and b are vectors (real valued) Ex. (3 elements)Pseudo code a = [a 1, a 2, a 3 ] T acc = 0; b = [b 1, b 2, b 3 ] T for i=1:3, c = a 1 *b 1 + a 2 *b 2 + a 3 *b 3 ; acc = acc + a[i]*b[i]; end; c = acc; Parallelism, Control & Communication How to combine with NIOS/MicroBlaze When is it beneficial etc

19 ASPI Introduction Vector Inner Product (2) Example algoritms FIR filter a represents the filter coefficients b represents the buffer of the signal to be filtered c represents the filtered signal Matrix multiplication may be described as a set of vector inner products. Several matrix operations may be described as sets of vector operations.

20 ASPI Introduction (Partial) design methodology Application/Algorithm Application/Algorithm Analysis Implementation(s) SW (PC/AD/ARM) HW(Xilinx/Altera) Implementation Analysis Suggestions for HW/SW partitioning Implementation SW + HW MicroBlaze/NiosII + Co-processor Implementation Analysis Project Work Details

21 ASPI Introduction Project Work Results See also slide

22 ASPI Introduction Lab Resources Available platforms: 1.2 RC100 boards (“small” Xilinx FPGA), 2.2 RC203 boards (“medium” Xilinx FPGA), 3.2 Altera boards (“medium” Altera FPGA), 4.TI and AD DSP boards (model ? quantity ?), 5.1 Lyrtech Signal-Master board (FPGA+DSP, no support!!!) Available development tools: 1.Celoxica DK3 design tools 2.Xilinx & Altera design tools

23 ASPI Introduction Reading suggestions/Articles Closely Coupled Co-processors for Algorithmic Acceleration Accelerating C Software Applications Applications of Reprogrammability in Algorithm Acceleration Algorithmic C Synthesis Fuels Functional Reuse Using Hardware Acceleration Units in Software Defined Radio Modem Functions Finding the best System Design Flow for a High-Speed JPEG Encoder From C software to FPGA hardware

24 ASPI Introduction Reading suggestions/Books 1.SpecC: Specification Language and Design MethodologySpecC: Specification Language and Design Methodology 2.System: Design: A Practical Guide with SpecC See also SpecC SystemSystem: Design: A Practical Guide with SpecCSpecC System 3.Embedded System Design: A Unified Hardware/Software IntroductionEmbedded System Design: A Unified Hardware/Software Introduction

25 ASPI Introduction Formation of project groups 1.Study project ideas carefully 2.Discuss with teachers 3.Prepare for Sept. 14th. a specific project proposal and a list of participants 4.Present your proposal at the next semester group meeting to be held at ???

26 ASPI Introduction ASPI Group Rooms, Home Page etc Group Rooms: 9ASPI12 studerende i 1 grupperum RUM: A6-108/ 36 m2 Home Page: Secretary: Dorthe Sparre Fredrik Bajers Vej 12, A5-214 Phone: Dorthe Sparre

27 ASPI Introduction 9th Semester Courses ASPI9-2A Hardware/Software Codesign Purposes: 1.Give the students the essential knowledge about problems related to the design of modern digital systems for various applications, in particular mobile applications. 2.Make the students understand how to apply digital electronic components efficiently in such systems. 3.Make the students able to apply a systematic design methodology to arrive at near-optimal implementations, using design tools for evaluating a large number of alternatives (Design Space Exploration, DSE).

28 ASPI Introduction 9th Semester Courses ASPI9-2B Hardware Platform Analysis, Compilation, and optimization Purposes: 1.To provide the students with: knowledge about one particular state-of-the-art IC technology, and comprehension about its usage in modern integrated system design. 2.To make the students understand and apply methods for synthe- sizing from a functional description to an optimal heterogeneous architecture in terms of physical size, execution time, and power consumption. 3.To provide comprehension on syntax and semantics of a specific modern Hardware Description Language (HDL). 4.To make the students able to apply the above topics in terms of formal methods for structures HW/SW Codesign.