Sonics Bus Modeling for Felix/VCC EE249 Project Presentation December 3, 1999 Mike Sheets

December 3, 1999Modeling Sonics in Felix/VCC2 Introduction What is involved in a bus model? Sonics two level arbitration scheme Modeling the arbiter in VCC Performance simulation Problems with the model

December 3, 1999Modeling Sonics in Felix/VCC3 Modeling in Felix/VCC Architecture exploration requires mapping behavior onto architecture SiliconBackplane is fundamentally a bus Bus models are fundamentally arbitration models Can model Sonics architecture by adding a new arbiter to VCC

December 3, 1999Modeling Sonics in Felix/VCC4 TDMA Arbitration Time Division Multiple Access Each slot is allocated to at most one transmitter Each slot has a fixed time duration Each frame contains n slots Frame repeats continuously … frame (length n) n-1 slot (time slice) 0123…

December 3, 1999Modeling Sonics in Felix/VCC5 Token Passing Arbitration Token Passing Arbitration (Round Robin) Token is passed in a predefined order Transmitter can only send when has token When finished transmitting, passes token on n-1 … current token owner

December 3, 1999Modeling Sonics in Felix/VCC6 Bus Arbitration Scheme Fixed slots Guaranteed bandwidth Potentially wasteful Tokens Guaranteed fair, but might slow down fast initiators Slot allocated when needed Round-robin (token passing) TDMA Reliability Flexibility

December 3, 1999Modeling Sonics in Felix/VCC7 Sonics Hybrid Arbitration Scheme Implemented as two tiers, slice (TDMA) and token (round robin) Owner of the slice gets right of refusal If owner not ready to send, uses token arbiter Can trade-off between slice, token, and both to balance reliability and flexibility

December 3, 1999Modeling Sonics in Felix/VCC8 Sonics Bus Model Flexible bandwidth arbitration model TDMA slot map gives slot owner right of refusal Unowned/unused slots fall to round-robin arbitration SBClk typically different from IClk and TClk so synchronization required Latency after slice granted is user-specified between 2-7 SBClk cycles Initiator Core Initiator Agent ProcessorClock synch., SB handshaking IClkSBClk Interconnect OCP Target Agent Target Core Clock synch., SB handshaking Memory, I/O ports SBClkTClk OCP Pipelined commands Posted writes Selectable read latency Sonics SiliconBackplaneSenderReceiver Arbiter

December 3, 1999Modeling Sonics in Felix/VCC9 Sonics Architecture Cores conform to Open Core Protocol (OCP) SiliconBackplane is synthesized by Sonics tools

December 3, 1999Modeling Sonics in Felix/VCC10 Behavioral Model Four initiator agents and four target agents in a daisy-chain Initiator agent access patterns are uniform pulse trains Target agents simply sink the data

December 3, 1999Modeling Sonics in Felix/VCC11 Hardware Mapping TestCores mapped to hardware cores Communication mapped to SiliconBackplane

December 3, 1999Modeling Sonics in Felix/VCC12 Arbitration Model in VCC Sender CTA Arbiter 1) Posted write Behaviors run continuously Receiver 2) Submit transaction 3) Complete transaction 4) Receive data instantaneoustime delay

December 3, 1999Modeling Sonics in Felix/VCC13 Communication Delay Model 1. Receive a bus transaction 2. Synchronize request to SiliconBackplane clock 3. Arbitrate multiple simultaneous requests to determine the correct time slice 4. Add SiliconBackplane pipeline delays 5. Notify communication complete

December 3, 1999Modeling Sonics in Felix/VCC14 Sonics Arbiter Parameters Bus parameters TDMA time-wheel counter maximums Token-passing order Bus frequency Initiator parameters (communication link) Arbitration policy (slice, token, both) TDMA look-up table (slot map) Minimum number of slots between requests

December 3, 1999Modeling Sonics in Felix/VCC15 Simulation Results Gantt charts show access pattern Legend

December 3, 1999Modeling Sonics in Felix/VCC16 Simulation Results (2) Statistics are provided in tabular form Bus utilization (total or per initiator) Arbitration mean latency (total or per initiator) Most/least utilized connection Results used to tweak arbitration parameters Arbitration policy, slot map, token ordering Bus frequency

December 3, 1999Modeling Sonics in Felix/VCC17 Queuing Receiver Communication Can be implemented using behavior framework Code generation for queue Estimation for queue Sender CTA Arbiter Posted write ReceiverQueue Data available Acknowledge handshake Posted writes can come at any rate

December 3, 1999Modeling Sonics in Felix/VCC18 Queuing Sender Communication Output queue behavior cannot be implemented using any current VCC framework Can fake it by adding CTA queues inside arbiter Problem is being addressed in a future version of VCC Receiver CTA Arbiter SenderQueue Need a handshake here, but the required signals are not available Posted writes can come at any rate

December 3, 1999Modeling Sonics in Felix/VCC19 Summary Sonics SiliconBackplane can be implemented as an arbiter model in VCC Mapping communication to the arbiter model yields useful bus utilization statistics Model is cycle accurate, but made fast by skipping unimportant cycles Queuing model in VCC has some problems