LCLS Control Group LCLS-Week Oct , 2005 BPM Signal Processing T. Straumann, M. Cecere, E. Medvedko, P. Krejcik SLAC B. Lill ANL

LCLS Control Group LCLS-Week Oct , 2005 Overview for Stripline BPMs Requirements/Engineering Constraints Status Current Frontend Design Timeline for next 12 months

LCLS Control Group LCLS-Week Oct , 2005 Objective High precision/resolution BPM Electronics 5um resolution (R ~ 12mm) drift < 5um/h low bunch charge: nC Stripline sensitivity: V = (a-b)/(a+b) = 2 r / R dynamic range > 60dB + 20dB

LCLS Control Group LCLS-Week Oct , 2005 Engineering Constraints SNR expressed as position noise (LINAC Stripline; 150MHz) dB[ r/1um ] = NF – dB[ q/1nC ] - ½ dB[ BW/1MHz ] 8dB > NF + 14dB(.2nC) – 10dB (10MHz) noise figure including cable losses stripline signal level based on estimation

LCLS Control Group LCLS-Week Oct , 2005 Baseband vs. Mixer Baseband Simpler Cheaper Use existing cables (?) Only marginally meets resolution requirements Mixer More signal at higher freq. Proven solution ADC performs better at IF LO generation + distribution New cables in LINAC needed

LCLS Control Group LCLS-Week Oct , 2005 System Overview Calibration scheme does not require extra cables Direct digitization

LCLS Control Group LCLS-Week Oct , 2005 Status VME Digitizers + basic driver software available Echotek Joerger SIS New card ordered (13ENOB, 130MSPS, 700MHz input BW) First frontend design + prototype (E. Medvedko) Engineer hired (M. Cecere)

LCLS Control Group LCLS-Week Oct , 2005 Frontend f 0 =150MHz (enough signal, ADC still well performing) Low noise, 10MHz BW Low distortion Alias suppression Build Prototype Test (noise, stability, out-of band performance, linearity) Final Design Interface (form factor, control signals, status monitors) Calibration

LCLS Control Group LCLS-Week Oct , 2005 BPM Analog Front End Baseband Design BPF # 1 Signal from BPM or Hybrid BPF # 2 LNA ADC Final Amplifier Undersampling ADC Frequency Selection Filter Low Noise Amplifier Band Pass Filter

LCLS Control Group LCLS-Week Oct , 2005 Baseband Design Component Selection Criteria BPF # 1 BPF # 2 LNA ADC Freq./BW determine SNR Low Insertion Loss Good OOB rejection Low NF Low Distortion Moderate Gain Sharp Rolloff (Anti- alias) Flat Passband High Gain*BW Low High Output Level >= 119MSPS High Dynamic Range BW>= 200MHz

LCLS Control Group LCLS-Week Oct , 2005 Timeline (Injector only)

LCLS Control Group LCLS-Week Oct , 2005 Calibration Bench Test Measurement setup (not worse than required stability!!) Test stability of calibration (splitters, BPM striplines) Cross-talk issues? Repeatability Multiplexing (t/f) Final design, integration

LCLS Control Group LCLS-Week Oct , 2005 LCLS Cavity BPM Overview RF BPM system current status Planning for prototype testing Planning for 8 LTU BPMs electrically identical to those in the undulator. Planning for 33 undulator BPMs

LCLS Control Group LCLS-Week Oct , 2005 Miteq X-Band Low Noise Receiver Existing product line WR 75 Waveguide Interface Low Noise Figure (2.7 dB) Prototype delivery date 12/10/05 Budgetary price for prototype $ (for 3 channels)

LCLS Control Group LCLS-Week Oct , 2005 Prototype Receiver Specification ParameterSpecification LimitCondition RF Frequency GHz 20.0 Celsius Dx, Dy, Intensity Input Peak Power50 watts peakNo damage (limiter protection) LO Frequency GHz (2856 MHz*4) /- 0.2 Celsius 1nC, 1mm offset, 200fs BL LO Power Range+10 dBm Max.Provide LO for 3 down converters IF Frequency60 MHz Min /- 0.2 Celsius Noise Figure Dx and DY2.7 dB Max /- 0.2 Celsius Noise Figure Intensity (reference)4.0 dB Max /- 0.2 Celsius LO to RF Isolation40 dB Min.20.0 Celsius LO to IF Isolation45 dB Min.20.0 Celsius Output Power+14 dBm1 dB compression Conversion Gain25 dB typical20.0 Celsius

LCLS Control Group LCLS-Week Oct , 2005 Long Lead Item Status Receiver Prototype del. 12/10/05 Local oscillator del. 11/24/05 Waveguide del. 12/1/05 Waveguide calibration kit del. 12/9/05 CPI Vacuum windows 11/30/05

LCLS Control Group LCLS-Week Oct , 2005 BPM System Test Approach Phase I Injector Test Stand ITS Install single X-Band Cavity and modified off- the-shelf down converter receiver Mount BPM on Piezo two-axis translation stage Phase II Bypass line test with PC gun Install three X-Band Cavities BPMs Bypass line test with PC gun to start June 06

LCLS Control Group LCLS-Week Oct , 2005 Charge- 1 nC single- bunch Bunch length- ~ ps FWHM for ps laser Spot size on final screen at 5.5 MeV ~ 0.75 mm rms, ps laser Injector Test Stand ITS Beam Parameters

LCLS Control Group LCLS-Week Oct , 2005 Phase I Data Acquisition Design Approach Instrument three channel down converters with Struck SIS ADCs 14-bit Single VME board will provide the data acquisition for 8 channels Epics driver complete Digitize horizontal, vertical position and Intensity 0 to 1 volt range Fit Data to decaying exponential at 60 MHz

LCLS Control Group LCLS-Week Oct , 2005 Phase I Testing Objectives Test prototype Cavity BPM, down converter, and data acquisition Generate preliminary compliance table to specification Gain operational experience to determine if translation stage is useful, what are optimum operating parameters

LCLS Control Group LCLS-Week Oct , 2005 Phase I Schedule Milestones Design and develop prototype Cavity BPM Prototype non vacuum Nov 05 Build single Cavity BPM Dec 05 Cold Test Dec 05 Install cavity BPM into ITS and Test Jan 06

LCLS Control Group LCLS-Week Oct , 2005 Phase II Schedule Milestones Refine design and develop First Article Cavity BPM and support hardware Jan 06 Build 3 Cavity BPMs Mar 06 Cold Test May 06 Install cavity BPM into APS PAR/Booster bypass line and Test June 06

LCLS Control Group LCLS-Week Oct , 2005 Phase II Testing Objectives First Article Prototypes evaluated Test three BPM separated by fixed TBD distance to determine single-shot Complete test matrix

LCLS Control Group LCLS-Week Oct , 2005 LTU and Undulator Planning Receiver and LO housed in shielded enclosure below girder 20 watt power dissipation maximum Presently BPM output on wall side BPM output flexible waveguide section allows movement for alignment

LCLS Control Group LCLS-Week Oct , 2005 BPM Mounting BPM connects directly to the girder. Mechanical translation stage used for alignment BPM and Quad can be pre-aligned independently with respect to each other

LCLS Control Group LCLS-Week Oct , 2005 Undulator Planning

LCLS Control Group LCLS-Week Oct , 2005 Backup slides

LCLS Control Group LCLS-Week Oct , 2005 f o = 150MHz BW = 10MHz Lark Engineering MS CC Insert. Loss = 5.8dB TTE filters KB3T-150M-10M-50-3A Insert. loss = 4.1dB Microwave Filter Co. 3MB10-150/10-SF/SF-1 Insertion loss = 3dB Sirenza SGA-6589 G = 26dB NF = 3.0dB OIP3 = 33dBm Sirenza SGA-4363 G = 18dB NF = 3.1dB OIP3 = 29dBm Sawtek fo= 150MHz BW = 10MHz Insert. loss = 11dB TI OPA847 GBW = 3.9GHz Distortion -105dBc LTC MSPSmax 16-bit 700MHz BW f samp =119MHz Req. jitter < 350fs AD MSPSmax 14-bit 200MHz BW f samp =102? Req. jitter < 600fs Alias 30MHz Baseband Design Components BPF # 1 BPF # 2 LNA ADC NF = 2-4dB NF = 3dB Cable NF = 2-4dB

LCLS Control Group LCLS-Week Oct , 2005 Input signal Cable losses BPF1 LNA BPF2 Final output Frequency MHz dBm BPM signal Baseband Design Frequency Response

LCLS Control Group LCLS-Week Oct , 2005 BPM or Hybrid LNA ADC RF LO IF MHz 43MHz xN 119MHz Minicircuits ZFM-2 1 – 1000 MHz Conv Loss = 5.8dB Mixer Based BPM Block Diagram

LCLS Control Group LCLS-Week Oct , 2005 Frequency MHz dBm BPM signal After coax BPF1 LNA BPF2 mixer Mixer Based Design Frequency Response

LCLS Control Group LCLS-Week Oct , 2005 Software Tasks Evaluation / test software BPM Processor Processing algorithm Real-time tasks: data acquisition and processing timing history buffers Calibration Integration (SLC-aware IOC, timing, feedback) Slow controls (gain, calib, status monitors, alarms)

LCLS Control Group LCLS-Week Oct , 2005 Integration; Hardware Clock generation and distribution Timing; triggers/gates Calibration signal generation and distribution Controls: gain, calib. mux Power Status monitors

LCLS Control Group LCLS-Week Oct , 2005 Integration; Software Timing SLC-aware layer Shot-to-shot feedback High-level applications (EPICS database) Naming Real-time Sysadmin; infrastructure; network

LCLS Control Group LCLS-Week Oct , 2005 PDRO local oscillator GHz (119 MHz x 96) Phase lock to 119 MHz ref 0 dBm +/- 3 dB +13 dBm output power In-Band Spurs <70 dBc Phase noise depends on 119 MHz reference

LCLS Control Group LCLS-Week Oct , 2005 Noise Estimates Sensitivity: -58 dBm/0.2nC/1  m Minimum bit size: nC Assumes 2 gain ranges for 75 dB Noise floor <200 nm rms ParameterValue Thermal noise-174 dBm/Hz IF Bandwidth20 MHz Noise in-band-101 dBm Receiver 1 dB compression +14 dBm Receiver gain25 dB Receiver noise figure2.7 dB

LCLS Control Group LCLS-Week Oct , 2005 APS Test Objectives Develop a cavity BPM that meets system requirements and can be manufactured economically Develop simulation model that correlates to prototype data Transition from prototyping to production

LCLS Control Group LCLS-Week Oct , 2005 ITS Installation

LCLS Control Group LCLS-Week Oct , 2005 Cost Savings Reduce the dipole cavity outputs from 4 ports to 2 ports Terminate the unused ports in vacuum Eliminate 2 transitions, 2 windows, waveguide, 2 magic tees Prove resolution and offset performance