Managing design complexity Partition of designs Typical design process using VHDL Test Bed A VHDL example

Large Scale Design

Design Data Management VHDL design data are organized as libraries. A library may contain any number of previously analyzed design units. The dependency relations among VHDL units are defined by the analysis order rather than the lexical order. A library is referred by its logical name. The mapping of a logical name into a file or a set of files on a disk is done by the VHDL toolset. Each VHDL implementation should support at least two library logical names: WORK and STD: –WORK = the current library during analysis. –STD = VHDL-defined library:

Design Data Management * The package STANDARD contains the definition of the basic types such as boolean, bit, character, severity_level, integer, real, time, etc. * The package TEXTIO contains a number of routines which are used to read and write ASCII files (and terminals). Access to external libraries is achieved by the library clause: library TTL_components; use TTL_components.Main_package. all

Name Visibility The following VHDL constructs create a new name space: –an entity declaration and its architecture body –a process statement –a block statement –a subprogram –a configuration declaration –a record type declaration –a loop statement –a component declaration A name declared within the current name space is visible from the point of its declaration until the end of the space. A name's visibility can be masked by nested constructs. The dot notation and the use clause are used to override the basic visibility rule. If name-crash happens, none of the names are visible.

Design Partitioning Structure decomposition: an entity may consists of several components which are instantiation of the next level entities. Behavioral decomposition: –Embedded subprograms definition in process (sup-port parallel-sequential* hierarchy) –Concurrent procedure calls (support also parallel-parallel- sequential* hierarchy) Ex. - It is very difficult to have sequential-parallel-sequential hierarchy in VHDL.

Design Systems with VHDL A complete VHDL design usually consists of the following three parts: –- an entity declaration –- an architectural body (or several) –- a test bench which consists of –* its entity declaration and –* its architecture body (mainly for stimuli definition) VHDL supports the top-down design methodology.

Design Systems with VHDL A typical design process could be: –Common data types and conversion functions are de-fined in a package. –The interface of the system is defined in an entity. –A behavioral description is developed to capture the functional specification of the system. –The design is partitioned by grouping behaviors together to form blocks and substituting them with components. –The details of the components can then be designed using the same strategy. Advantages of this approach: –Each intermediate result of the design process can be simulated to make sure that it is correct in respect to the original specification.

An Example: Traffic Light Controller

An Example: Traffic Light Controller (cont’d)

First partition of Traffic Light Controller

Test-Bed

Test bed

State Diagram for Control Process

VHDL for Control Process (example 1)

VHDL for Control Process (example 2)

Structural VHDL for Control Process

Sources Krzysztof Kuchcinski