Project Checkpoint Implementing library support for the Virgil programming language Ryan Hall Advisor: Jens Palsberg March 14, 2007

Outline Proposed accomplishments by checkpoint Actual accomplishments by checkpoint Difficulties/Surprises/Deviations What do I expect to do next

Proposed Accomplishments Learn Virgil and Avrora simulator ~ 1 week Run Blink program on actual mote ~ 1 week Driver support for sensor and serial port ~ 6 weeks Run drivers on actual mote ~ 1 week

Actual Accomplishments Learn Virgil and Avrora simulator (account setup, etc.) ~ 2 week Analog to Digital Converter driver ~ 2 weeks Run Blink program/ADC driver on actual mote ~ 1 week USART0 driver ~ 3 weeks Create USART1 driver from USART1 ~ 1 week

Difficulties Avrora learning curve Implemented ADC driver in 2 days Spent 1 week debugging it with no luck Learned the power of monitors and call traces Only took 1 day to debug after that Virgil language syntax Delegates, raw types, etc. Lack of debugging features No exceptions thrown (null, out of bounds, etc.)

Surprises Surprised ADC worked on mote! Covering sensor changed LED output Did not think debugging the code would be so difficult Thought Virgil would have implemented helpful debugging tools (exceptions) Simulator didn’t even work part of the time! Hard to track down where the problem is

Deviations Involvement in what is a priority for Virgil Most of my “The thought I had this week” revolved around making Virgil better These thoughts are usually derived from frustration in writing drivers Now there exists a Virgil monitor in Avrora that outputs the Virgil exception Null and out of bound checks (especially null!)

Next Step Run USART drivers on actual motes Learn the how to talk to board serial port ~ 1 week Actually get them run Simulator ignores most configuration bits ~ 1 week (hopefully) Begin building wrappers around drivers to implement the Radio, Serial Port and Sensor All must have unified interface

References

Questions?