Retiming. Consider the Following Circuit Suppose T XOR = 3 ns, T pcq = 1 ns, T setup = 1 ns, then this circuit can be clocked at 1 ns + (3 x 3 ns) + 1.

Slides:



Advertisements
Similar presentations
CS 140 Lecture 11 Sequential Networks: Timing and Retiming Professor CK Cheng CSE Dept. UC San Diego 1.
Advertisements

1 ECE734 VLSI Arrays for Digital Signal Processing Chapter 3 Parallel and Pipelined Processing.
Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Sequential Synthesis.
Chapter 4 Retiming.
Review Binary Search Trees Operations on Binary Search Tree
CHAPTER 3 Sequential Logic/ Circuits.  Concept of Sequential Logic  Latch and Flip-flops (FFs)  Shift Registers and Application  Counters (Types,
Sequential Timing Optimization. Long path timing constraints Data must not reach destination FF too late s i + d(i,j) + T setup  s j + P s i s j d(i,j)
Assume array size is 256 (mult: 4ns, add: 2ns)
Computability and Complexity 23-1 Computability and Complexity Andrei Bulatov Search and Optimization.
Complexity 15-1 Complexity Andrei Bulatov Hierarchy Theorem.
Spring 07, Apr 10, 12 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Constraint Graph and Performance Optimization.
Circuit Retiming with Interconnect Delay CUHK CSE CAD Group Meeting One Evangeline Young Aug 19, 2003.
Combining Technology Mapping and Retiming EECS 290A Sequential Logic Synthesis and Verification.
CSE 140L Lecture 4 Flip-Flops, Shifters and Counters Professor CK Cheng CSE Dept. UC San Diego.
Pipelining and Retiming 1 Pipelining  Adding registers along a path  split combinational logic into multiple cycles  increase clock rate  increase.
Spring 08, Feb 28 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Retiming Vishwani D. Agrawal James J. Danaher.
Embedded Systems Hardware:
Penn ESE Fall DeHon 1 ESE (ESE534): Computer Organization Day 19: March 26, 2007 Retime 1: Transformations.
Is the following graph Hamiltonian- connected from vertex v? a). Yes b). No c). I have absolutely no idea v.
EE290A 1 Retiming of AND- INVERTER graphs with latches Juliet Holwill 290A Project 10 May 2005.
Continuous Retiming EECS 290A Sequential Logic Synthesis and Verification.
Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Constraint Graph and Performance Optimization.
Spring 07, Apr 5 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Retiming Vishwani D. Agrawal James J. Danaher Professor.
EDA (CS286.5b) Day 19 Covering and Retiming. “Final” Like Assignment #1 –longer –more breadth –focus since assignment #2 –…but ideas are cummulative –open.
1 Retiming Outline: ProblemProblem FormulationFormulation Retiming algorithmRetiming algorithm.
Embedded Systems Hardware: Storage Elements; Finite State Machines; Sequential Logic.
ECE Synthesis & Verification 1 ECE 667 ECE 667 Synthesis and Verification of Digital Systems Retiming.
Chapter #6: Sequential Logic Design 6.2 Timing Methodologies
EDA (CS286.5b) Day 18 Retiming. Today Retiming –cycle time (clock period) –C-slow –initial states –register minimization.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 8: February 13, 2008 Retiming.
TECH Computer Science Graph Optimization Problems and Greedy Algorithms Greedy Algorithms  // Make the best choice now! Optimization Problems  Minimizing.
Introduction to Graph Theory
Spring 2010, Feb 10...ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2010 Constraint Graph and Retiming Solution Vishwani.
Some Useful Circuits Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University.
T Flip-Flop A T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when the two inputs are tied together. When T =
Lecture 5. Sequential Logic 3 Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System Education & Research.
Binary Search From solving a problem to verifying an answer.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 24: April 18, 2011 Covering and Retiming.
Spring 2014, Feb 14...ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2014 Constraint Graph and Retiming Solution Vishwani.
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 7: February 3, 2002 Retiming.
Unit 9: Coping with NP-Completeness
1 A Min-Cost Flow Based Detailed Router for FPGAs Seokjin Lee *, Yongseok Cheon *, D. F. Wong + * The University of Texas at Austin + University of Illinois.
Timing Analysis Section Delay Time Def: Time required for output signal Y to change due to change in input signal X Up to now, we have assumed.
ANALYSIS OF SEQUENTIAL CIRCUITS by Dr. Amin Danial Asham.
ELEC692 VLSI Signal Processing Architecture Lecture 3
1 Retiming and Re-synthesis Outline: RetimingRetiming Retiming and Resynthesis (RnR)Retiming and Resynthesis (RnR) Resynthesis of PipelinesResynthesis.
Pipelining and Retiming
CALTECH CS137 Spring DeHon 1 CS137: Electronic Design Automation Day 5: April 12, 2004 Covering and Retiming.
Introduction to Graph Theory
Homework 1 Problem 1: (5 points) Both Dijkstras algorihm and Bellmanford Algorithm generates shortest paths to all destinations. Modify the algorithm to.
1 COMP541 Sequential Logic Timing Montek Singh Sep 30, 2015.
1) Find and label the degree of each vertex in the graph.
Graphs Definition: a graph is an abstract representation of a set of objects where some pairs of the objects are connected by links. The interconnected.
Iterative Improvement for Domain-Specific Problems Lecturer: Jing Liu Homepage:
Retiming EECS 290A Sequential Logic Synthesis and Verification.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 25: April 17, 2013 Covering and Retiming.
De Bruijn sequences 陳柏澍 Novembers Each of the segments is one of two types, denoted by 0 and 1. Any four consecutive segments uniquely determine.
Vishwani D. Agrawal James J. Danaher Professor
CS137: Electronic Design Automation
James D. Z. Ma Department of Electrical and Computer Engineering
ELEC 7770 Advanced VLSI Design Spring 2012 Retiming
Vishwani D. Agrawal James J. Danaher Professor
ESE535: Electronic Design Automation
G1. G1 g2 g3 g4 g5 g6 g8 g10 g11 g12 g14.
Connectivity Section 10.4.
Jun Chen and Changbo Long
CS184a: Computer Architecture (Structures and Organization)
ESE535: Electronic Design Automation
ELEC 7770 Advanced VLSI Design Spring 2016 Retiming
Timing Analysis and Optimization of Sequential Circuits
Presentation transcript:

Retiming

Consider the Following Circuit Suppose T XOR = 3 ns, T pcq = 1 ns, T setup = 1 ns, then this circuit can be clocked at 1 ns + (3 x 3 ns) + 1 ns = 11 ns. D-FF X Y Z F XOR D-FF

Why Are They Not Equivalent? Suppose FFs are initialized to 0 D-FF X Y Z F XOR D-FF X Y Z F XOR D-FF P Z Y X F Z Y X F

Are These Equivalent? Suppose FFs are initialized to 0 D-FF X Y Z F XOR D-FF X Y Z F XOR D-FF P Z Y X F Z Y X F fewer D-FF But same delay

Basic Idea of Retiming X D-FF If you have 2 FFs at the inputs, you can move it to the output Or if you have a FF at the output, you can move it to the inputs In general, can move N FFs from inputs to output, and vice versa Y D-FF F X Y F

Example XOR How to move FFs around to minimize clock period? (assuming T pcq = T setup = 0)

Graph Model Vertex vi, combinational node, delay = d(vi) All inputs and outputs connect through a faux node “host” with d(host) = 0 Edge e(vi, vj) or eij, weight wij = number of flip-flops between vi and vj

Path Delay and Path Weight A set of connected nodes specify a path Path delay = ∑ d(vi) = comb. delay of path Path weight = ∑ wij = # FFs along the path Retiming of a node i denoted by an integer ri –It represents the number of registers moved across, initially ri = 0 –Register moved from output to input, ri → ri + 1 –Register moved from input to output, ri → ri – 1 –After retiming, edge weight wij’ = wij + rj – ri

9 Example a b c d e f g h Initial retiming vector = {0,0,0,0,0,0,0,0} Critical path delay = 10 r(h)=0 r(b)=0r(c)=0r(d)=0 r(e)=0 r(f)=0 r(g)=0 0 r(a)= 0

Retimed Example → →0 1 1 a b c d e f g h Optimal retiming vector = {-1,-1,-2,-2,-2,-1,0,0} Critical path delay = 5 0 r(h)=0 r(a)= –1r(b)= – 1r(c)= –2r(d)= –2 r(e)= –2 r(f)= –1 r(g)=0

Optimized Circuit XOR

Retiming Theorem Given a network G(V, E) and a cycle time T, (r1, r2,... ) is a feasible retiming if and only if: ri – rj ≤ wij for all edges ri – rj ≤ W(vi, vj) – 1 for all node-pairs (vi, vj) such that D(vi, vj) > T where W(vi, vj) is the minimum weight path between vi and vj D(vi, vj) is the maximum delay among all minimum weight paths between vi and vj. Above is a Linear Program, which can tested for feasibility for a given T. Binary search over possible cycle time T.

Retiming & Resynthesis

Initial State X 0 What should be the new initial state? Y 0 F X Y F 0

Cannot Always Recover Initial State Cannot always get exactly the same initial state behavior on the retimed circuit For some applications, a startup transient may not be a problem ?