Providing Performance Guarantees in Multipass Network Processors Isaac KeslassyKirill KoganGabriel ScalosubMichael Segal TechnionCisco & BGU (Ben-Gurion.

Slides:



Advertisements
Similar presentations
Real-Time Mutli-core Scheduling Moris Behnam. Introduction Single processor scheduling – E.g., t 1 (P=10,C=5), t 2 (10, 6) – U= >1 – Use a faster.
Advertisements

Bio Michel Hanna M.S. in E.E., Cairo University, Egypt B.S. in E.E., Cairo University at Fayoum, Egypt Currently is a Ph.D. Student in Computer Engineering.
Michael Markovitch Joint work with Gabriel Scalosub Department of Communications Systems Engineering Ben-Gurion University Bounded Delay Scheduling with.
The 9th Israel Networking Day 2014 Scaling Multi-Core Network Processors Without the Reordering Bottleneck Alex Shpiner (Technion/Mellanox) Isaac Keslassy.
An Optimal Lower Bound for Buffer Management in Multi-Queue Switches Marcin Bieńkowski.
CSC457 Seminar YongKang Zhu December 6 th, 2001 About Network Processor.
Competitive Analysis of Buffer Policies with SLA Commitments Boaz Patt-Shamir, Tel Aviv University Gabriel Scalosub, University of Toronto Yuval Shavitt,
1 Statistical Analysis of Packet Buffer Architectures Gireesh Shrimali, Isaac Keslassy, Nick McKeown
Nick McKeown CS244 Lecture 6 Packet Switches. What you said The very premise of the paper was a bit of an eye- opener for me, for previously I had never.
Dynamic Internet Congestion with Bursts Stefan Schmid Roger Wattenhofer Distributed Computing Group, ETH Zurich 13th International Conference On High Performance.
A Scalable Switch for Service Guarantees Bill Lin (University of California, San Diego) Isaac Keslassy (Technion, Israel)
Making Parallel Packet Switches Practical Sundar Iyer, Nick McKeown Departments of Electrical Engineering & Computer Science,
Providing Performance Guarantees in Multipass Network Processors Isaac KeslassyKirill KoganGabriel ScalosubMichael Segal EE, TechnionCISCO & CSE, BGU.
1 A Tree Based Router Search Engine Architecture With Single Port Memories Author: Baboescu, F.Baboescu, F. Tullsen, D.M. Rosu, G. Singh, S. Tullsen, D.M.Rosu,
Chapter 8 – Processor Scheduling Outline 8.1 Introduction 8.2Scheduling Levels 8.3Preemptive vs. Nonpreemptive Scheduling 8.4Priorities 8.5Scheduling Objectives.
CS 3013 & CS 502 Summer 2006 Scheduling1 The art and science of allocating the CPU and other resources to processes.
1 Architectural Results in the Optical Router Project Da Chuang, Isaac Keslassy, Nick McKeown High Performance Networking Group
Competitive Buffer Management with Packet Dependencies Alex Kesselman, Google Boaz Patt-Shamir, Tel Aviv University Gabriel Scalosub, University of Toronto.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion MSM.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion The.
Guaranteed Smooth Scheduling in Packet Switches Isaac Keslassy (Stanford University), Murali Kodialam, T.V. Lakshman, Dimitri Stiliadis (Bell-Labs)
October 5th, 2005 Jitter Regulation for Multiple Streams David Hay and Gabriel Scalosub Technion, Israel.
Competitive Buffer Management with Packet Dependencies Alex Kesselman, Google Boaz Patt-Shamir, Tel Aviv University Gabriel Scalosub, University of Toronto.
Chain: Operator Scheduling for Memory Minimization in Data Stream Systems Authors: Brian Babcock, Shivnath Babu, Mayur Datar, and Rajeev Motwani (Dept.
Computer Networking Lecture 17 – Queue Management As usual: Thanks to Srini Seshan and Dave Anderson.
Wk 2 – Scheduling 1 CS502 Spring 2006 Scheduling The art and science of allocating the CPU and other resources to processes.
School of Information Technologies IP Quality of Service NETS3303/3603 Weeks
Real-Time Operating System Chapter – 8 Embedded System: An integrated approach.
Online Packet Switching Techniques and algorithms Yossi Azar Tel Aviv University.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Maximal.
7/15/2015HY220: Ιάκωβος Μαυροειδής1 HY220 Schedulers.
Pipelined Two Step Iterative Matching Algorithms for CIOQ Crossbar Switches Deng Pan and Yuanyuan Yang State University of New York, Stony Brook.
A Scalable, Cache-Based Queue Management Subsystem for Network Processors Sailesh Kumar, Patrick Crowley Dept. of Computer Science and Engineering.
Distributed Real-Time systems 1 By: Mahdi Sadeghizadeh Website: Sadeghizadeh.ir Advanced Computer Networks.
CIS679: Scheduling, Resource Configuration and Admission Control r Review of Last lecture r Scheduling r Resource configuration r Admission control.
CS640: Introduction to Computer Networks Aditya Akella Lecture 20 - Queuing and Basics of QoS.
ATM SWITCHING. SWITCHING A Switch is a network element that transfer packet from Input port to output port. A Switch is a network element that transfer.
Advance Computer Networking L-5 TCP & Routers Acknowledgments: Lecture slides are from the graduate level Computer Networks course thought by Srinivasan.
Budapest University of Technology and Economics Department of Telecommunications and Media Informatics Optimized QoS Protection of Ethernet Trees Tibor.
Scheduling policies for real- time embedded systems.
Scheduling Example 3 (1) Assume: FIFO Job Scheduling 100 K Main Memory Processor Sharing Process Scheduling (Cont…)
Competitive Queue Policies for Differentiated Services Seminar in Packet Networks1 Competitive Queue Policies for Differentiated Services William.
ISLIP Switch Scheduler Ali Mohammad Zareh Bidoki April 2002.
Packet Forwarding. A router has several input/output lines. From an input line, it receives a packet. It will check the header of the packet to determine.
Packet Scheduling and Buffer Management Switches S.Keshav: “ An Engineering Approach to Networking”
IEEE HPSR 2014 Scaling Multi-Core Network Processors Without the Reordering Bottleneck Alex Shpiner (Technion / Mellanox) Isaac Keslassy (Technion) Rami.
Opportunistic Traffic Scheduling Over Multiple Network Path Coskun Cetinkaya and Edward Knightly.
Michael Schapira Yale and UC Berkeley Joint work with P. Brighten Godfrey, Aviv Zohar and Scott Shenker.
Florida State UniversityZhenhai Duan1 BCSQ: Bin-based Core Stateless Queueing for Scalable Support of Guaranteed Services Zhenhai Duan Karthik Parsha Department.
CS640: Introduction to Computer Networks Aditya Akella Lecture 20 - Queuing and Basics of QoS.
Final Chapter Packet-Switching and Circuit Switching 7.3. Statistical Multiplexing and Packet Switching: Datagrams and Virtual Circuits 4. 4 Time Division.
Guaranteed Smooth Scheduling in Packet Switches Isaac Keslassy (Stanford University), Murali Kodialam, T.V. Lakshman, Dimitri Stiliadis (Bell-Labs)
Multimedia and QoS#1 Quality of Service Support. Multimedia and QoS#2 QOS in IP Networks r IETF groups are working on proposals to provide QOS control.
High-Speed Policy-Based Packet Forwarding Using Efficient Multi-dimensional Range Matching Lakshman and Stiliadis ACM SIGCOMM 98.
Loss-Bounded Analysis for Differentiated Services. By Alexander Kesselman and Yishay Mansour Presented By Sharon Lubasz
T. S. Eugene Ngeugeneng at cs.rice.edu Rice University1 COMP/ELEC 429 Introduction to Computer Networks Lecture 18: Quality of Service Slides used with.
CSCI1600: Embedded and Real Time Software Lecture 23: Real Time Scheduling I Steven Reiss, Fall 2015.
Minimizing Delay in Shared Pipelines Ori Rottenstreich (Technion, Israel) Joint work with Isaac Keslassy (Technion, Israel) Yoram Revah, Aviran Kadosh.
Queue Scheduling Disciplines
Topics in Internet Research: Project Scope Mehreen Alam
Block-Based Packet Buffer with Deterministic Packet Departures Hao Wang and Bill Lin University of California, San Diego HSPR 2010, Dallas.
Competitive Queueing Policies for QoS Switches Nir Andelman Yishay Mansour An Zhu TAUTAUStanford.
scheduling for local-area networks”
QoS & Queuing Theory CS352.
Packet Forwarding.
Queue Management Jennifer Rexford COS 461: Computer Networks
Chapter 8 – Processor Scheduling
IEEE Student Paper Contest
Brian Babcock, Shivnath Babu, Mayur Datar, and Rajeev Motwani
An Optimal Lower Bound for Buffer Management in Multi-Queue Switches
Presentation transcript:

Providing Performance Guarantees in Multipass Network Processors Isaac KeslassyKirill KoganGabriel ScalosubMichael Segal TechnionCisco & BGU (Ben-Gurion University) BGU

Network Processors (NPs) NPs used in routers for almost everything – Forwarding – Classification – DPI – Firewalling – Traffic engineering Classical NP architectures Homogeneous tasks  Increasingly heterogeneous demands Examples: VPN encryption, LZS decompression, advanced QoS, … What are “classical NP architectures”? 2

Pipelined NP Architecture Each packet gets processed by a pipeline of PPEs (packet processing engines) – each PPE in charge of a different task  main issues: hard to scale, synchronous, packet header copy 3 PPE Packet Header Buffer E.g., Xelerated X11 NP

Parallel/Multi-Core NP Architecture Each packet is assigned to a single PPE – single PPE performs all processing, in “run-to-completion”  main issue: run-to-completion  heavy packets can starve light ones 4 PPE Hybrid Architecture: Pipeline + Multi-core E.g., Cavium CN68XX NP E.g., EZChip NP-4 NP

Multipass NP Architecture Packet processing divided into processing cycles Packet headers recycled into the queue after each processing cycle Main benefits: – More scalable – Asynchronous – No run-to-completion (heavy packets do not necessarily starve light ones)  Main issue : many degrees of freedom (more complex scheduling) 5 E.g., Cisco QuantumFlow NP PPE Packet Header Buffer

Scheduling in Multipass NP Packets have heterogeneous demands – Each packet might require a different number of cycles Designer objective: guarantee minimum throughput – Minimum number of processed packets per second Problem: many degrees of freedom – Buffer management: FIFO, priority queueing, …? Preemption upon full buffer? – For each packet: what PPEs? In what order? – Fairness? – No reordering? – Heterogeneous PPEs? 6 PPE Packet Header Buffer

Assumptions Focusing on buffer management policy – Efficiently use the full buffer size (unit-size packets with slotted time) Only 1 PPE – Complex enough! Each packet needs up to k passes – Number of passes known for each packet – k used in analysis, not in algorithm Our goal: competitive worst-case throughput guarantee – For any input sequence σ, show that Throughput(σ) ≥ OPT(σ) / c – Arbitrary arrival sequences (adversarial…) 7

PPE Buffer Management Policies PPE PQ (Priority queueing) less work = higher priority FIFO 1

A Case for Preemption Assume non-preemption – when a packet arrives to a full buffer, it is dropped FIFO lower bound – simple traffic pattern: competitive ratio is  (k) PQ lower bound – (much) more involved – also  (k) 9 (OR, how bad can non-preemption be when buffer overflows?) Matching O(k) upper bounds for both

What If We Preempt? 10 PPE Example:

What If We Preempt? Preemption + PQ = Optimal – PQ can serve as a benchmark for optimality Preemption + FIFO? – not optimal:  (log k) lower bound – sublinear(k) upper bound: still open 11

Are Preemptions Free? New packets “cost” more than recycled packets – Example: costly memory access and system updates (pointers, data- structures) Copying cost  – each new packet admitted incurs a cost of  [0,1) Objective: – maximize ( Throughput – Cost ) 12

Algorithm PQ  13 PPE When buffer full, accept new packet if it needs less cycles than (worst packet / β) 13 Example: β =2

Algorithm PQ  Competitive ratio: f(k, ,  ) Gives some best  for each value of k and  14 (1-  ) (1 + log  /(  -1) (k/2) + log  (k)) 1-  log  (k)

Simulation Results Single PPE (C=1), copying cost  =0.4 – ON-OFF bursty traffic 15 PQ is NOT optimal anymore! k

Conclusion Multipass NP architecture model Preemptions help significantly If preemptions are not free, schedule optimality gets complicated 16

Thank you.