Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt1 Lecture 14 Sequential Circuit ATPG Simulation-Based Methods (Lecture 13alt in the Alternative.

Slides:



Advertisements
Similar presentations
Feb. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 141 Lecture 14 Sequential Circuit ATPG Simulation-Based Methods n Use of fault simulation for test generation.
Advertisements

ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Sequential circuit ATPG.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 13/12alt1 Lecture 13 Sequential Circuit ATPG Time-Frame Expansion (Lecture 12alt in the Alternative.
1 Lecture 10 Sequential Circuit ATPG Time-Frame Expansion n Problem of sequential circuit ATPG n Time-frame expansion n Nine-valued logic n ATPG implementation.
Copyright 2001, Agrawal & BushnellLecture 3b: Testability Analysis1 VLSI Testing Lecture 3b: Testability Analysis n Definition n Controllability and observability.
Nov. 21, 2006ATS'06 1 Spectral RTL Test Generation for Gate-Level Stuck-at Faults Nitin Yogi and Vishwani D. Agrawal Auburn University, Department of ECE,
1 Lecture 14 Sequential Circuit ATPG Simulation-Based Methods n Use of fault simulation for test generation n Contest n Directed search n Cost functions.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 71 Lecture 7 Fault Simulation n Problem and motivation n Fault simulation algorithms n Serial n Parallel.
Lecture 20 Delay Test (Lecture 17alt in the Alternative Sequence)
Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, AL 36849
A Diagnostic Test Generation System Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama USA Nov. 3rdITC
May 11, 2006High-Level Spectral ATPG1 High-Level Test Generation for Gate-level Fault Coverage Nitin Yogi and Vishwani D. Agrawal Auburn University Department.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt1 Lecture 8 Testability Measures n Definition n Controllability and observability n SCOAP measures.
6/11/2015A Fault-Independent etc…1 A Fault-Independent Transitive Closure Algorithm for Redundancy Identification Vishal J. Mehta Kunal K. Dave Vishwani.
Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4b1 Design for Testability Theory and Practice Lecture 4b: Fault Simulation n Problem and motivation.
Copyright 2001, Agrawal & BushnellDay-1 PM-2 Lecture 51 Testing Analog & Digital Products Lecture 5: Testability Measures n Definition n Controllability.
Dec. 19, 2005ATS05: Agrawal and Doshi1 Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849,
Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA Vishwani D. Agrawal Alok S. Doshi.
Spring 08, Apr 1 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Testability Measures Vishwani D. Agrawal James.
Aug 11, 2006Yogi/Agrawal: Spectral Functional ATPG1 Spectral Characterization of Functional Vectors for Gate-level Fault Coverage Tests Nitin Yogi and.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt1 Lecture 9alt Combinational ATPG (A Shortened version of Original Lectures 9-12) n ATPG problem.
Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 61 Design for Testability Theory and Practice Lecture 6: Combinational ATPG n ATPG problem n Example.
6/17/2015Spectral Testing1 Spectral Testing of Digital Circuits An Embedded Tutorial Vishwani D. Agrawal Agere Systems Murray Hill, NJ 07974, USA
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 11alt1 Lecture 11alt Advances in Combinational ATPG Algorithms  Branch and Bound Search  FAN – Multiple.
Lecture 5 Fault Simulation
Jan. 9, 2007 VLSI Design Conference Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department.
Dec. 29, 2005Texas Instruments (India)1 Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849,
1 Oct 24-26, 2006 ITC'06 Fault Coverage Estimation for Non-Random Functional Input Sequences Soumitra Bose Intel Corporation, Design Technology, Folsom,
9/21/04ELEC / Class Projects 1 ELEC / /Fall 2004 Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and.
Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Fault Simulation Vishwani D. Agrawal James J.
January 16, '02Agrawal: Delay testing1 Delay Testing of Digital Circuits Vishwani D. Agrawal Agere Systems, Murray Hill, NJ USA
Partial Scan Design with Guaranteed Combinational ATPG Vishwani D. Agrawal Agere Systems, Circuits and Systems Research Lab Murray Hill, NJ 07974, USA.
Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt1 Lecture 20alt DFT: Partial, Random-Access & Boundary Scan n Definition n Partial-scan architecture.
1 Spectral BIST Alok Doshi Anand Mudlapur. 2 Overview Introduction to spectral testing Previous work – Application of RADEMACHER – WALSH spectrum in testing.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 81 Lecture 8 Testability Measures n Origins n Controllability and observability n SCOAP measures 
Independence Fault Collapsing and Concurrent Test Generation Thesis Advisor: Vishwani D. Agrawal Committee Members: Victor P. Nelson, Charles E. Stroud.
Oct. 5, 2001Agrawal, Kim and Saluja1 Partial Scan Design With Guaranteed Combinational ATPG Vishwani D. Agrawal Agere Systems Processor Architectures and.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 241 Lecture 24 Design for Testability (DFT): Partial-Scan & Scan Variations n Definition n Partial-scan.
11/17/04VLSI Design & Test Seminar: Spectral Testing 1 Spectral Testing Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer.
Jan. 11, '02Kim, et al., VLSI Design'021 Mutiple Faults: Modeling, Simulation and Test Yong C. Kim University of Wisconsin, Dept. of ECE, Madison, WI 53706,
March 6, th Southeastern Symposium on System Theory1 Transition Delay Fault Testing of Microprocessors by Spectral Method Nitin Yogi and Vishwani.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 101 Lecture 10 Combinational ATPG and Logic Redundancy n Redundancy identification n Redundancy removal.
VLSI Testing Lecture 7: Combinational ATPG
March 8, 2006Spectral RTL ATPG1 High-Level Spectral ATPG for Gate-level Circuits Nitin Yogi and Vishwani D. Agrawal Auburn University Department of ECE.
10/14/2015 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Testability Measures.
An Iterative Heuristic for State Justification in Sequential Automatic Test Pattern Generation Aiman H. El-MalehSadiq M. SaitSyed Z. Shazli Department.
Vishwani D. Agrawal Auburn University, Dept. of Elec. & Comp. Engg. Auburn, AL 36849, U.S.A. Nitin Yogi NVIDIA Corporation, Santa Clara, CA th.
Copyright 2001, Agrawal & BushnellLecture 6: Sequential ATPG1 VLSI Testing Lecture 6: Sequential ATPG n Problem of sequential circuit ATPG n Time-frame.
Copyright 2001, Agrawal & BushnellLecture 6:Fault Simulation1 VLSI Testing Lecture 6: Fault Simulation Dr. Vishwani D. Agrawal James J. Danaher Professor.
Fault Models, Fault Simulation and Test Generation Vishwani D. Agrawal Department of ECE, Auburn University Auburn, AL 36849, USA
November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan1 Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns Nitin Yogi.
Fault Models, Fault Simulation and Test Generation Vishwani D. Agrawal Department of ECE, Auburn University Auburn, AL 36849, USA
Lecture 14 Sequential Circuit ATPG Simulation-Based Methods
VLSI Testing Lecture 4: Testability Analysis
VLSI Testing Lecture 6: Fault Simulation
Algorithms and representations Structural vs. functional test
Lecture 7 Fault Simulation
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES
Definition Partial-scan architecture Historical background
Lecture 13 Sequential Circuit ATPG Time-Frame Expansion
VLSI Testing Lecture 6: Fault Simulation
VLSI Testing Lecture 7: Combinational ATPG
Lecture 10 Sequential Circuit ATPG Time-Frame Expansion
VLSI Testing Lecture 8: Sequential ATPG
VLSI Testing Lecture 7: Combinational ATPG
Aiman H. El-Maleh Sadiq M. Sait Syed Z. Shazli
VLSI Testing Lecture 7: Delay Test
Lecture 14 Sequential Circuit ATPG Simulation-Based Methods
Lecture 13 Sequential Circuit ATPG Time-Frame Expansion
Presentation transcript:

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt1 Lecture 14 Sequential Circuit ATPG Simulation-Based Methods (Lecture 13alt in the Alternative Sequence) n Use of fault simulation for test generation n Contest n Directed search n Cost functions n Genetic Algorithms n Spectral Methods n Summary

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt2 Motivation n Difficulties with time-frame method: n Long initialization sequence n Impossible to guarantee initialization with three-valued logic (Section 5.3.4) n Circuit modeling limitations n Timing problems – tests can cause races/hazards n High complexity n Inadequacy for asynchronous circuits n Advantages of simulation-based methods n Advanced fault simulation technology n Accurate simulation model exists for verification n Variety of tests – functional, heuristic, random n Used since early 1960s

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt3 A Test Causing Race Z A B C s-a-1 Z’ A’ B’ C’ s-a-1 Time-frame 0 Time-frame /0 0 X X Test is a two-vector sequence: X0, 11 10, 11 is a good test; no race in fault-free circuit 00, 11 causes a race condition in fault-free circuit

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt4 Using Fault Simulator Fault simulator Vector source: Functional (test-bench), Heuristic (walking 1, etc.), Weighted random, random Fault list Test vectors New faults detected? Stopping criteria (fault coverage, CPU time limit, etc.) satisfied? Stop Update fault list Append vectors Restore circuit state Generate new trial vectors Yes No Yes No Trial vectors

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt5 Background n Seshu and Freeman, 1962, Asynchronous circuits, parallel fault simulator, single-input changes vectors. n Breuer, 1971, Random sequences, sequential circuits n Agrawal and Agrawal, 1972, Random vectors followed by D-algorithm, combinational circuits. n Shuler, et al., 1975, Concurrent fault simulator, random vectors, sequential circuits. n Parker, 1976, Adaptive random vectors, combinational circuits. n Agrawal, Cheng and Agrawal, 1989, Directed search with cost-function, concurrent fault simulator, sequential circuits. n Srinivas and Patnaik, 1993, Genetic algorithms; Saab, et al., 1996; Corno, et al., 1996; Rudnick, et al., 1997; Hsiao, et al., 1997.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt6 Contest n A Concurrent test generator for sequential circuit testing (Contest). n Search for tests is guided by cost-functions. n Three-phase test generation: n Initialization – no faults targeted; cost-function computed by true-value simulator. n Concurrent phase – all faults targeted; cost function computed by a concurrent fault simulator. n Single fault phase – faults targeted one at a time; cost function computed by true-value simulation and dynamic testability analysis. n Ref.: Agrawal, et al., IEEE-TCAD, 1989.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt7 Directed Search Cost=0 Vector space Tests Initial vector Trial vectors

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt8 Cost Function n Defined for required objective (initialization or fault detection). n Numerically grades a vector for suitability to meet the objective. n Cost function = 0 for any vector that perfectly meets the objective. n Computed for an input vector from true-value or fault simulation.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt9 Phase I: Initialization n Initialize test sequence with arbitrary, random, or given vector or sequence of vectors. n Set all flip-flops in unknown ( X ) state. n Cost function:  Cost = Number of flip-flops in the unknown state  Cost computed from true-value simulation of trial vectors n Trial vectors: A heuristically generated vector set from the previous vector(s) in the test sequence; e.g., all vectors at unit Hamming distance from the last vector may form a trial vector set. n Vector selection: Add the minimum cost trial vector to the test sequence. Repeat trial vector generation and vector selection until cost becomes zero or drops below some given value.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt10 Phase II: Concurrent Fault Detection n Initially test sequence contains vectors from Phase I. n Simulate all faults and drop detected faults. n Compute a distance cost function for trial vectors:  Simulate all undetected faults for the trial vector.  For each fault, find the shortest fault distance (in number of gates) between its fault effect and a PO.  Cost function is the sum of fault distances for all undetected faults. n Trial vectors: Generate trial vectors using the unit Hamming distance or any other heuristic. n Vector selection:  Add the trial vector with the minimum distance cost function to test sequence.  Remove faults with zero fault distance from the fault list.  Repeat trial vector generation and vector selection until fault list is reduced to given size.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt11 Distance Cost Function 0 s-a Initial vector Trial vectors Trial vectors Trial vectors Distance cost function for s-a-0 fault Minimum cost vector Fault detected

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt12 Concurrent Test Generation Vector space Test clusters Initial vector

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt13 Need for Phase III Vector space Initial vector

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt14 Phase III: Single Fault Target n Cost (fault, input vector) = K x AC + PC  Activation cost (AC) is the dynamic controllability of the faulty line.  Propagation cost (PC) is the minimum (over all paths to POs) dynamic observability of the faulty line.  K is a large weighting factor, e.g., K = 100.  Dynamic testability measures (controllability and observability) are specific to the present signal values in the circuit.  Cost of a vector is computed for a fault from true-value simulation result.  Cost = 0 means fault is detected. n Trial vector generation and vector selection are similar to other phases.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt15 Dynamic Test. Measures n Number of inputs to be changed to achieve an objective:  DC0, DC1 – cost of setting line to 0, 1  AC = DC0 (or DC1) at fault site for s-a-1 (or s-a-0)  PC – cost of observing line n Example: A vector with non-zero cost (DC0,DC1) = (1,0) (0,1) (1,0) (0,2) (1,0) s-a-0 Cost(s-a-0, 10) = 100 x = 201 AC = 2 PC = 1

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt16 Dynamic Test. Measures n Example: A vector (test) with zero cost (DC0,DC1) = (0,1) (1,0) (0,1) (1,0) (0,2) (1,0) s-a-0 Cost(s-a-0, 01) = 100 x = 0 AC = 0 PC = 0

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt17 Other Features n More on dynamic testability measures: n Unknown state – A signal can have three states. n Flip-flops – Output DC is input DC, plus a large constant (say, 100), to account for time frames. n Fanout – PC for stem is minimum of branch PCs. n Types of circuits: Tests are generated for any circuit that can be simulated: n Combinational – No clock; single vector tests. n Asynchronous – No clock; simulator analyzes hazards and oscillations, 3-states, test sequences. n Synchronous – Clocks specified, flip-flops treated as black-boxes, 3-states, implicit-clock test sequences.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt18 Contest Result: s5378 n 35 PIs, 49 POs, 179 FFs, 4,603 faults. n Synchronous, single clock. Contest 75.5% 0 1,722 57,532 3 min.* 9 min.* Random vectors 67.6% 0 57, min. Gentest** 72.6% hrs. 10 sec. Fault coverage Untestable faults Test vectors Trial vectors used Test gen. CPU time# Fault sim. CPU time# # Sun Ultra II, 200MHz CPU *Estimated time **Time-frame expansion (higher coverage possible with more CPU time)

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt19 Genetic Algorithms (GAs) n Theory of evolution by natural selection (Darwin, )  C. R. Darwin, On the Origin of Species by Means of Natural Selection, London: John Murray,  J. H. Holland, Adaptation in Natural and Artificial Systems, Ann Arbor: University of Michigan Press,  D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning, Reading, Massachusetts: Addison-Wesley,  P. Mazumder and E. M. Rudnick, Genetic Algorithms for VLSI Design, Layout and Test Automation, Upper Saddle River, New Jersey: Prentice Hall PTR, n Basic Idea: Population improves with each generation.  Population  Fitness criteria  Regeneration rules

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt20 GAs for Test Generation n Population: A set of input vectors or vector sequences. n Fitness function: Quantitative measures of population succeeding in tasks like initialization and fault detection (reciprocal to cost functions.) n Regeneration rules (heuristics): Members with higher fitness function values are selected to produce new members via transformations like mutation and crossover.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt21 Strategate Results s1423 s5378 s35932 Total faults 1,515 4,603 39,094 Detected faults 1,414 3,639 35,100 Fault coverage 93.3% 79.1% 89.8% Test vectors 3,943 11, CPU time 1.3 hrs hrs hrs. HP J MB Ref.: M. S. Hsiao, E. M. Rudnick and J. H. Patel, “Dynamic State Traversal for Sequential Circuit Test Generation,” ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 5, no. 3, July 2000.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt22 Spectral Methods Replace with compacted vectors Test vectors (initially random vectors) Fault simulation-based vector compaction Stopping criteria (coverage, CPU time, vectors) satisfied? Extract spectral characteristics (e.g., Hadamard coefficients) and generate vectors Stop Append new vectors Compacted vectors No Yes

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt23 Spectral Information n Random inputs resemble noise and have low coverage of faults. n Sequential circuit tests are not random:  Some PIs are correlated.  Some PIs are periodic.  Correlation and periodicity can be represented by spectral components, e.g., Hadamard coefficients. n Vector compaction removes unnecessary vectors without reducing fault coverage:  Reverse simulation for combinational circuits (Example 5.5.)  Vector restoration for sequential circuits. n Compaction is similar to noise removal (filtering) and enhances spectral characteristics.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt24 Spectral Method: s5378 Simulation-based methods Time-frame expansion Spectral-method* Strategate Contest Hitec Gentest Fault cov % 79.06% 75.54% 70.19% 72.58% Vectors ,571 1, CPU time 43.5 min hrs min hrs. 5.0 hrs. Platform Ultra Sparc 10 Ultra Sparc 1 Ultra II HP9000/J200 Ultra II * A. Giani, S. Sheng, M. S. Hsiao and V. D. Agrawal, “Efficient Spectral Techniques for Sequential ATPG,” Proc. IEEE Design and Test in Europe (DATE) Conf., March 2001.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14/13alt25 Summary n Fault simulation is an effective tool for sequential circuit ATPG. n Tests can be generated for any circuit that can be simulated. Timing considerations allow dealing with asynchronous circuits. n Simulation-based methods generate better tests but produce more vectors, which can be reduced by compaction. n A simulation-based method cannot identify untestable faults. n Spectral methods hold potential.