Spring 2006EE VLSI Design II - © Kia Bazargan 187 EE 5324 – VLSI Design II Kia Bazargan University of Minnesota Part IV: Control Path and Busses

Spring 2006EE VLSI Design II - © Kia Bazargan 188 References and Copyright Textbooks referenced  [WE92] N. H. E. Weste, K. Eshraghian “Principles of CMOS VLSI Design: A System Perspective ” Addison-Wesley, 2 nd Ed.,  [Rab96] J. M. Rabaey “Digital Integrated Circuits: A Design Perspective ” Prentice Hall, 1996.

Spring 2006EE VLSI Design II - © Kia Bazargan 189 References and Copyright (cont.) Slides used(Modified by Kia when necessary)  [©Hauck] © Scott A. Hauck, ; G. Borriello, C. Ebeling, S. Burns, 1995, University of Washington  [©Prentice Hall] © Prentice Hall 1995, © UCB 1996 Slides for [Rab96]

Spring 2006EE VLSI Design II - © Kia Bazargan 190 What is Control Logic? Data paths  Actual input values are not important Movement of data from one point to another or standard computation (e.g., shift register, add, logical XOR, etc.) Control logic  Input values matter and cause state and output transitions Used to control flow of data in data path logic (e.g., load a register, select addition or subtraction in ALU, etc.) [©Hauck]

Spring 2006EE VLSI Design II - © Kia Bazargan 191 Control Path Input to control path  Program (from RAM, ROM, PLA, …)  Condition codes (from datapath) Implementation  Usually state machine Datapath Control Logic Control signals (func. sel) Data-dependent conditions (e.g., overflow)

Spring 2006EE VLSI Design II - © Kia Bazargan 192 Control Path Example A control path to control a simple data path Datapath operations:  2’s complement numbers  add, sub, inc, dec, compare (< and =), bit-wise XOR Control signals:  Encoding of 7 operations (minimum of 3 signals) Condition codes:  zero, negative, overflow, underflow [©Hauck]

Spring 2006EE VLSI Design II - © Kia Bazargan 193 Control Path Example: Operation Details Subtraction:  Addition with complemented input and carry-in of 1 A – B  A + (B' +1)2's complement form Increment:  Addition with one input equal to all 0 and carry-in of 1 A + 1  A Decrement:  subtraction with one input equal to all 1 and carry-in of 0 A – 1  A  A + 0' Comparison:  Subtraction and test if carry-out (>) or result is zero (=) A < B  A – B with a negative result A = B  A – B result equal to 0 [©Hauck]

Spring 2006EE VLSI Design II - © Kia Bazargan 194 Control Path Example: Implementation Carry chain opzeroBcompBC 0 outsel add1001 sub1111 inc0011 dec0101 comp111– XOR10–0 outputs: R (result) S n-1 (sign bit) Z (zero detect) < if S n-1 = 1 = if zero detect = C i+1 CiCi complement B input zero B input (active low) Ai Bi Ri Si select output (sum, XOR) zero detect g p [©Hauck]

Spring 2006EE VLSI Design II - © Kia Bazargan 195 Datapath Components:  data storage, arithmetic and logic operators, shifters, stacks,... Characteristics:  Wide data transfers (regularity)  Many-to-many connections (busses)  Large capacitances (busses)  Critical path (arithmetic and carry propagation) Control signals must direct the flow of data between data path elements and busses 32 register file shifter ALUI / O 32

Spring 2006EE VLSI Design II - © Kia Bazargan 196 Busses and Precharging In data paths and in memory arrays in particular:  Busses get very long and heavy  Large capacitance due to wire length and the transistor drains Not easy to implement complementary structure:  Due to geographic distribution of inputs Common solution:  Pre-charge the bus  Only one half of the complementary structure needs to be considered

Spring 2006EE VLSI Design II - © Kia Bazargan 197 Precharged Bus Example 22 Cbus L1 11 L2 11 L3 11

Spring 2006EE VLSI Design II - © Kia Bazargan 198 Tri-State Bus If you can guarantee that at most one source will write to the bus at a time, can use tri-state busses: Cbus L1 L2 L3