1 CALICE D4 simulation results G.Villani feb. 06 Cell size: 25 x 25 m 2 Epitaxial thickness: 20 m Diode location: S4 Diode size: 1.5 x 1.5 m 2 Cell 2Cell 3 Cell 4 Cell 5 Cell 6 Cell 9 Cell 8 Cell Cell 1 Diode bias: 2VPWell bias: 0V Substrate bias: floating 10 hits simulated: mirroring over central cell and transformation over 3 x 3 cells allows surface reconstruction of Q coll (x,y) Cell := enclosing of 4 diodes whose Charge add (as in cell 5)
2 CALICE D4 simulation results G.Villani feb. 06 thickness singlemulti 15 m 20 m
3 Surface Q coll (x,y) Normalized surface Q coll (x,y) vs. max(Qcoll(x,y)) CALICE D4 simulation results G.Villani feb Single diode Q coll (x,y) hit 1 Sum diode Q coll (x,y) hit 1 Epitaxial thickness: 20 μm Q coll (x,y) = 1092
4 Contour plot of cell charge at different % of total collected charge 20% 40% 60% 80% Increasing number of threshold levels reduces spatial error Minimum error around ≈ 57 % ( need further analysis) Normalized surface Q coll (x,y) vs. max(Qcoll(x,y)) CALICE D4 simulation results G.Villani feb. 06 Epitaxial thickness: 20 μm
5 Surface Q coll (x,y) Normalized surface Q coll (x,y) vs. max(Qcoll(x,y)) CALICE D4 simulation results G.Villani feb Single diode Q coll (x,y) hit 1 Sum diode Q coll (x,y) hit 1 Epitaxial thickness: 15 μm Surface Q coll (x,y) Q coll (x,y) = 1122
6 Contour plot of cell charge at different % of total collected charge 20% 40% 60% 80% Increasing number of threshold levels reduces spatial error Minimum error around ≈ 57 % ( need further analysis) Normalized surface Q coll (x,y) vs. max(Qcoll(x,y)) CALICE D4 simulation results G.Villani feb. 06 Epitaxial thickness: 15 μm
7 Maximum signal around e - when Σ Effect of spread of charge can be limited by increasing number of levels threshold Is there an ‘optimum’ thickness of epitaxial layer ? Conclusions CALICE D4 simulation results G.Villani feb. 06
8 Collection with different thicknesses 15 μm 20 μm