System-Level Verification –a Comparison of Approach Ray Turner Rapid Systems Prototyping, IEEE International Workshop on

What’s problem? The system designers are often faced with serious project delay when they wait for first silicon to begin software debugging. The objective of system level verification is to make the hardware and software debugging tasks as concurrent as possible. Addressed with intelligent trade-offs in changing the hardware or software,possibly avoiding: A degradation in product functionality. Reduced performance. An increase in product cost.

Introduction There a verity of approaches to system-level verification objectives performance requirement. Describe four different approaches to system verification and the trade-offs of each approach. Example s from actual projects will be used to demonstrate the application of each approach. Recommendations for determining the best verification approach are also given.

Verifying the entire system In a traditional approach, the verification of system under development is composed of –Custom ASIC, FPGA Separately simulation –Standard microprocessor and custom software verification After it appears that the board in working properly. The bugs in the ASIC and hardware/software interfaces  Too late in the product development cycle to implement an optional correction

System verification attempts to… –Verify all element of the design in a parallel fashion –Allowing interface bug s to be discovered early in the development cycle when the system partitioning is still fluid enough to allow for optimal choices to be made for fixing the problem. Verifying the entire system(cont.)

Verification is most frequently performed via simulation of the using a test bench. For more complex designs requiring a very large set of test vectors to cover it adequately, emulation is often used. Emulation has the additional advantage of allowing verification of the entire system with “real” data from a system environment. Testing of a design in the context of actual data and with thousands of time the volume of test data provides exceptionally high confidence in design correctness. Verifying the entire system(cont.)

Another important approach for system-level verification is the type of model available for the microprocessor The type of case –A stand processor being put on a board –A processor core bond-out chip being included in an ASIC The processor model can also be a Instruction Set Simulation(IIS)-a computer software model of the processor Verifying the entire system(cont.)

Models may be: –Clock-cycle-accurate Support verification of hardware to the processor include memory. –Bus-cycle-accurate Allow the verification of hardware and software interactions as well as processor-ASIC interaction. –Instruction-accurate Generally used for verifying the logic and mathematics of software execution. Verifying the entire system(cont.)

The more detail or accurate the model the lower the performance. Different models may be used during the verification the verification of different parts of the system: –Clock-cycle –accurate models Performance is low but relatively few cycle s are needed to verify correct interface between processor, memory and ASIC Verifying the entire system(cont.)

–Instruction-accurate When software is developed concurrently,it is used to verify non-hardware-specific sections of their code –verifying program logic and mathematics. Provide high performance,but cannot by themselves verify software interaction with the hardware. –Bus-cycle-accurate(Bus Functional Model) Provide mid-range performance and are most useful Verifying the software and interaction with the hardware Verifying the entire system(cont.)

There are commercial products: –Eagle from Synopsys –Seamless from Mentor Graphics That create a connection between an ISS and logic simulator. Providing the ability to simulate the ability to simulate the ASIC and other hardware component in complete detail,while running the processor and memory at a very high level of abstraction. Allowing detailed verification of the ASIC and its interaction with the software Verifying the entire system(cont.)

An additional alternative is to use an HDL model of the processor in the logic simulator. Some processor core vender will provide HDL model so that user can verify the entire ASIC which includes the core. Other vendors will not provide HDL models because of their highly proprietary nature. An HDL model also allows high performance emulation when silicon is not yet available. Verifying the entire system(cont.)

Approaches to co-verification Use a logic simulator for the entire design,using an HDL model of the processor and memory and putting the complied software. Use an ISS connection interface and logic simulator. Use an ISS,connection interface and emulator Use an emulator,a target system, and MP- ICE system

System-level verification using a logic simulator

System-level verification using an ISS connection interface and logic simulator.

System-level verification using an ISS,connection interface and emulator

System-Level verification using an emulator,a target system,and an MP-ICE system

Comparison of verification approach

Performance comparison

Conclusion In order to meet ever tighter project schedules and avoid disastrous last-minute surprises it is essential to verify the entire system The chart below shows the relative performance of the approaches described, although performance can vary greatly. As the software content of system s increases over the next several years,emulation will become more widely used due to it’s high performance.