4-to-1 Multiplexer: case Statement Discussion D2.3 Example 6.

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4-to-1 Multiplexer: case Statement Discussion D2.3 Example 6

4-to-1 Multiplexer z 4 x 1 MUX s0s1 c0 c1 c2 c3 z s1s0 0 0 c0 0 1 c1 1 0 c2 1 1 c3

-- Example 6: 4-to-1 MUX using case statement library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux41c is port( c : in STD_LOGIC_VECTOR(3 downto 0); s : in STD_LOGIC_VECTOR(1 downto 0); z : out STD_LOGIC ); end mux41c; architecture mux41c of mux41c is begin mx41_1: process (s, c) begin case s is when "00" => z <= c(0); when "01" => z <= c(1); when "10" => z <= c(2); when "11" => z <= c(3); when others => z <= c(0); end case; end process mx41_1; end mux41c; Must include ALL possibilities in case statement Note implies operator =>

Aldec Active-HDL Simulation