11/10/2004EE 42 fall 2004 lecture 301 Lecture #30 Finite State Machines Last lecture: –CMOS fabrication –Clocked and latched circuits This lecture: –Finite State Machines

11/10/2004EE 42 fall 2004 lecture 302 Finite State Machines The digital model we are looking at is an implementation of a finite state machine. A FSM has several states, corresponding to the values of each of the registers. Inputs into the machine are combined with the current state of the machine to determine the next state of the machine. Most complex digital systems are made from one or more finite state machines, because they can be more easily analyzed than asynchronous digital logic

11/10/2004EE 42 fall 2004 lecture 303 Block diagram This is a block diagram of a particular kind of FSM. (a Mealy machine with delayed outputs) Inputs (N) outputs Clock Current state of the system: Q(M) Clock Combinatorial Logic Register (N+M edge triggered flip-flops)

11/10/2004EE 42 fall 2004 lecture 304 Timing diagram for synchronous FSM Clock Inputs State Output Logic

11/10/2004EE 42 fall 2004 lecture 305 A computer as a FSM A computer could be viewed as a FSM, or you could view just the CPU as a FSM, accesses from the main memory as outputting addresses, followed by input of data from the memory, etc. A CPU might also be viewed as several interacting FSMs. –An accumulator –A memory interface unit –An instruction sequencer

11/10/2004EE 42 fall 2004 lecture 306 State Transition tables It is implicit that transitions occur only at discrete times (such as clock edges) StateInputNext stateOutput (received 6 bits so far) Next bitReceived 7 bits so far none (received 7 bits so far) Next bitHave received byte The byte received

11/10/2004EE 42 fall 2004 lecture 307 Defining State Machines Example: Suppose I am playing a game by tossing a coin. If I toss 3 heads in a row, I win. If I toss a tail before tossing three heads, I lose. States = {0_heads, 1_head, 2_heads} Inputs = {head, tail, absent} Outputs = {win, lose, absent} initialState = 0_heads

11/10/2004EE 42 fall 2004 lecture 308 Defining State Machines: Table This state machine can be defined using a table: (s(n+1), y(n)) = update(s(n), x(n)) x(n) = headx(n) = tail s(n) = 0_heads s(n) = 1_head s(n) = 2_heads Output absent means that there is no output at this transition There is a more visually appealing way to define the update function: a state diagram. (1_head, absent)(0_heads, lose) (2_heads, absent)(0_heads, lose) (0_heads, win) (0_heads, lose)

11/10/2004EE 42 fall 2004 lecture 309 Defining State Machines: State Diagram To create a state diagram for a state machine, first draw circles representing the states. 0_heads 1_head2_heads For each combination of input and state, draw an arrow from the current state to the next state. Label the arrow with the input and output that create the transition as shown: “input/output” head / absent tail / lose head / win

11/10/2004EE 42 fall 2004 lecture 3010 State Machines: State Response The state response is sequence of states resulting from a particular input sequence. Example: Find the state response and output sequence for x = 0_heads 1_head2_heads head / absent tail / lose head / win tailhead tail

11/10/2004EE 42 fall 2004 lecture 3011 Facts About State Machines The state machines addressed here are called Mealy machines. Mealy machines generate outputs during state transitions. Moore machines generate output while the system is in a particular state (output depends on state only). Each transition and output depends only on the current state and current input. Previous input elements only affect the transitions and output insofar as they determine the current state. A transition will be defined for every possible combination of input and current state.

11/10/2004EE 42 fall 2004 lecture 3012 Deterministic vs Nondeterministic For the state machines studied in this lecture, there is exactly one possible transition for each combination of current state and input. These state machines are called deterministic. Sometimes it is useful to model a system using a state machine that has more than one possible transition for each combination of current state and input. These state machines are called non- deterministic.

11/10/2004EE 42 fall 2004 lecture 3013 FSMs in programs The finite state machine model can be useful in the design of software as well as the design of hardware. If a program is responding to external events, which are not happening in a controlled order, a FSM description of the program can describe its high level operation better than sequential descriptions.

11/10/2004EE 42 fall 2004 lecture 3014 Implementing Sequential Logic Sequential Circuits –Simple circuits with feedback –Latches –Edge-triggered flip-flops Timing Methodologies –Cascading flip-flops for proper operation –Clock skew Asynchronous Inputs –Metastability and synchronization Basic Registers –Shift registers

11/10/2004EE 42 fall 2004 lecture 3015 Sequential Circuits Circuits with Feedback –Outputs = f(inputs, past inputs, past outputs) –Basis for building "memory" into logic circuits State is memory State is an "output" and an "input" to combinational logic Combination storage elements are also memory

11/10/2004EE 42 fall 2004 lecture 3016 X1 X2 Xn switching network Z1 Z2 Zn Circuits with Feedback Need to stop values from cycling around endlessly

11/10/2004EE 42 fall 2004 lecture 3017 R S Q Q' R S Q R' S' Q Q Q' S' R' Memory with Cross-coupled Gates Cross-coupled NOR gates –Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) Cross-coupled NAND gates –Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0)

11/10/2004EE 42 fall 2004 lecture 3018 Reset Hold Set Reset Race R S Q \Q 100 Timing Behavior R S Q Q'

11/10/2004EE 42 fall 2004 lecture 3019 Q(t+  ) R S Q(t) SRQ(t)Q(t+  ) X 111X hold reset set not allowed characteristic equation Q(t+  ) = S + R’ Q(t) R-S Latch Analysis Break feedback path R S Q Q' X1X1X1X1 Q(t) R S

11/10/2004EE 42 fall 2004 lecture 3020 enable' S' Q' Q R' R S Gated R-S Latch Control when R and S inputs matter –Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored Set Reset S' R' enable' Q Q' 100

11/10/2004EE 42 fall 2004 lecture 3021 period duty cycle (in this case, 50%) Clocks Used to keep time –Wait long enough for inputs (R' and S') to settle –Then allow to have effect on value stored Clocks are regular periodic signals –Period (time between ticks) –Duty-cycle (time clock is high between ticks - expressed as % of period)

11/10/2004EE 42 fall 2004 lecture 3022 clock R' and S' changingstablechangingstable Clocks (cont’d) Controlling an R-S latch with a clock –Can't let R and S change while clock is active (allowing R and S to pass) –Only have half of clock period for signal changes to propagate –Signals must be stable for the other half of clock period clock' S' Q' Q R' R S

11/10/2004EE 42 fall 2004 lecture 3023 clock R SQ Q'R SQ R S Cascading Latches Connect output of one latch to input of another How to stop changes from racing through chain? –Need to control flow of data from one latch to the next –Advance from one latch per clock period –Worry about logic between latches (arrows) that is too fast

11/10/2004EE 42 fall 2004 lecture 3024 Master-Slave Structure Break flow by alternating clocks (like an air-lock) –Use positive clock to latch inputs into one R-S latch –Use negative clock to change outputs with another R-S latch View pair as one basic unit –master-slave flip-flop –twice as much logic –output changes a few gate delays after the falling edge of clock but does not affect any cascaded flip-flops master stage slave stage P P' CLK R SQ Q'R SQ R S

11/10/2004EE 42 fall 2004 lecture 3025 Set 1s catch S R CLK P P' Q Q' Reset Master Outputs Slave Outputs The Catching Problem In first R-S stage of master-slave FF –0-1-0 glitch on R or S while clock is high "caught" by master stage –Leads to constraints on logic to be hazard-free master stage slave stage P P' CLK R SQ Q'R SQ R S

11/10/2004EE 42 fall 2004 lecture gates D Flip-Flop Make S and R complements of each other –Eliminates catching problem –Can't just hold previous value (must have new value ready every clock period) –Value of D just before clock goes low is what is stored in flip-flop –Can make R-S flip-flop by adding logic to make D = S + R' Q D Q Q' master stage slave stage P P' CLK R SQ Q'R SQ

11/10/2004EE 42 fall 2004 lecture 3027 Q D Clk=1 R S 0 D’ 0 D Q’ negative edge-triggered D flip-flop (D-FF) 4-5 gate delays must respect setup and hold time constraints to successfully capture input characteristic equation Q(t+1) = D holds D' when clock goes low holds D when clock goes low Edge-Triggered Flip-Flops More efficient solution: only 6 gates –sensitive to inputs only near edge of clock signal (not while high)