Design Technology Center National Tsing Hua University 2006 International Center on Design for Nanotechnologies Workshop Grand Formosa Taroko Grand Formosa.

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Presentation transcript:

Design Technology Center National Tsing Hua University 2006 International Center on Design for Nanotechnologies Workshop Grand Formosa Taroko Grand Formosa Taroko Jan. 6 - Jan. 7 Jan. 6 - Jan. 7

積體電路設計技術研發中心積體電路設計技術研發中心 2 議程 part Ⅰ DateTimeSessions JAN. 6 (Fri.) 08:15-08:30 Welcome and Introductions 08:30-10:30 Invited session on nanotechnologies (Chairs: Tim Cheng and Jason Cong) ** Nano-architectonics for Integrated Circuits and Systems - A Perspective (Kang Wang, UCLA) (Kang Wang, UCLA)Kang Wang, UCLAKang Wang, UCLA ** National Technology Program in Taiwan (Jyuo-Min Shyu, ITRI) Jyuo-Min ShyuJyuo-Min Shyu ** Research Highlights of CNST of UST (Cheng-Chung Chi, NTHU) Cheng-Chung Chi, NTHUCheng-Chung Chi, NTHU 10:30-10:45 Coffee Break 10:45-12:00 Design and Test for Reliability (Chair: Tim Cheng) ** Self-Adaptable and Error-Resilient System Design (Tim Cheng, UCSB) Tim ChengTim Cheng ** A New Paradigm for Scan Chain Diagnosis Using Signal Processing Techniques ( Shi-Yu Huang, NTHU) Techniques ( Shi-Yu Huang, NTHU)Shi-Yu Huang, NTHUShi-Yu Huang, NTHU ** Flash Memory Built-In Self-Diagnosis with Test Mode Contrl (Jen-Chieh Jen-Chieh Yeh, NTHU Yeh, NTHU) Yeh, NTHU) Yeh, NTHU 12:00-13:00Lunch

積體電路設計技術研發中心積體電路設計技術研發中心 3 議程 part Ⅱ DateTimeSessions Jan. 6 (Fri.) 13:00-14:15 Design and Test for Programmability (Chair: Shih-Chieh Chang NTHU) ** A BIST scheme for FPGA interconnect delay faults (Yen-Lin Peng, Yen-Lin Peng,Yen-Lin Peng, NTHU NTHU) NTHU) NTHU ** Maximum Instantaneous Current analysis and cross talk optimization *** A Bus Architecture for Crosstalk Elimination ( Wen-Wen Hsieh, *** A Bus Architecture for Crosstalk Elimination ( Wen-Wen Hsieh,Wen-Wen HsiehWen-Wen Hsieh NTHU) NTHU) *** Lower Bound Estimation of Maximum Instantaneous Current for *** Lower Bound Estimation of Maximum Instantaneous Current for Sequential Circuits (Cheng-Tao Hsieh, NTHU) Sequential Circuits (Cheng-Tao Hsieh, NTHU)Cheng-Tao Hsieh, NTHUCheng-Tao Hsieh, NTHU ** A probabilistic approach to logic equivalence checking (Chun-Yao Chun-Yao Wang, NTHU Wang, NTHU) Wang, NTHU) Wang, NTHU 14:15-14:30 Coffee Break 14:30-15:00 NSF/NSC discussion (Bill Chang and Cheng-Wen Wu, NTHU) Bill Chang Cheng-Wen WuBill Chang Cheng-Wen Wu 15:00-16:00 Education and social impact (Chair: Jason Cong) Joy of speech making (C.L. Liu, NTHU) C.L. Liu, NTHUC.L. Liu, NTHU 16:30-17:30 Panel discussions Opportunities and challenges for design for nanotechnologies 18:00-20:00Dinner

積體電路設計技術研發中心積體電路設計技術研發中心 4 議程 part Ⅲ DateTimeSessions JAN.7(Sat.) 08:30-09:00 Design Drivers (Steve Lin and/or Cheng Xu) Design Drivers (Steve Lin and/or Cheng Xu) 09:00-10:15 Complexity management for nano-scale designs Complexity management for nano-scale designs ** System-level synthesis for programmable systems (Jason Cong) ** System-level synthesis for programmable systems (Jason Cong)Jason CongJason Cong ** Solution Space Smoothing Method and its Application (Sheqin ** Solution Space Smoothing Method and its Application (SheqinSheqin Dong Dong) Dong) Dong 10:15-10:30 Coffee Break Coffee Break 10:30-11:30 Discussion of 2006 research plan Discussion of 2006 research plan 11:30-13:30 Lunch Lunch