On-Chip Structures for the 1.6 and 0.6  m Designs 1.6  m chip Final layout

On-Chip Structures for the 1.6 and 0.6  m Designs 0.6  m chip Final layout

On-Chip Structures for the 1.6 and 0.6  m Designs Close-up of the border ring oscillator for the 1.6  m chip: Two inverters on the right

On-Chip Structures for the 1.6 and 0.6  m Designs 1.6  m chip 19-stage ring osc. 0.6  m chip 31-stage ring osc.

On-Chip Structures for the 1.6 and 0.6  m Designs 4-bit counter design with T-flip flops for the 1.6  m chip

On-Chip Structures for the 1.6 and 0.6  m Designs 6-bit counter design with D-flip flops for the 1.6  m chip (“Cntout” is the most significant bit.)

On-Chip Structures for the 1.6 and 0.6  m Designs T flip-flop design using a D flip-flop and logic D flip-flop schematic using transmission gates, NAND gates and inverters

On-Chip Structures for the 1.6 and 0.6  m Designs D flip-flop layout from the 1.6  m chip

On-Chip Structures for the 1.6 and 0.6  m Designs Crosstalk testing structure on the 0.6  m chip: schematic and layout.