Network-on-Chip Examples System-on-Chip Group, CSE-IMM, DTU.

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Network-on-Chip Examples System-on-Chip Group, CSE-IMM, DTU

© System-on-Chip Group, CSE-IMM, DTU 2 NoC Research Overview

© System-on-Chip Group, CSE-IMM, DTU 3 Case Study ÆTHEREAL Xpipes CHAIN SPIN Nostrum …

© System-on-Chip Group, CSE-IMM, DTU 4 ÆTHEREAL Developed at Philips is a NoC that provides guaranteed throughput (GT) along side best-effort (BE) service All routers in the network have a common sense of time, and the routers forward traffic based on slot allocation. GT traffic is connection-oriented, and next hop information is provided within the packet BE traffic makes use of non-reserved slots BE packets are used to program the GT slots of the routers. Buffering: input queuing is implemented using custom-made hardware fifos, to keep the area costs down NA: provides support for many core interface such as AXI, DLT and support for connection oriented narrowcast and multicast

© System-on-Chip Group, CSE-IMM, DTU 5 ×pipes and ×pipesCompiler Developed by University of Bologna and Stanford University Xpipes a relatively fine-grain soft-macros of switches and pipelined links A go-back-N retransmission strategy is implemented as part of link-level error control Overall, delay for a flit to traverse from across one link and node is 2N+M cycles where N is number of pipeline stages and M is switch stages ×pipesCompiler is a tool to automatically instantiate an application specific custom communication infrastructure using ×pipes components It has been tested by creating both regular mesh and irregular topologies for three video processing applications Results show marginal difference in terms of power usage between the two topologies for the application execution time

© System-on-Chip Group, CSE-IMM, DTU 6 CHAIN Developed at the University of Manchester Implemented entirely using asynchronous circuit techniques exploit low power capabilities Targeted for heterogeneous low power systems, in which the network is system specific It makes use of 1-of-4 encoding, and source routes BE packets It has been implemented in smart cards Recent work from the group involved with CHAIN concerns prioritization in asynchronous networks

© System-on-Chip Group, CSE-IMM, DTU 7 SPIN (Scalable Programmable Integrated Network) Developed by Guerrier and Greiner Implements a fat-tree topology with two one- way 32bit datapaths links Packets are sent (via wormhole) as a sequence of flits each of size 4 bytes Three types of flits; first, data and last. The performance of the network under uniform randomly distributed load shows that the protocol accounts for about 31% of the total throughput, a relatively large overhead.

© System-on-Chip Group, CSE-IMM, DTU 8 Nostrum Developed at KTH in Stockholm has evolved from a system-level chip design approach Proposes a grid-based, router-driven communication media Guaranteed services are provided by so called looped containers Containers are implemented via virtual circuits, using an explicit time division multiplexing mechanism which they call Temporally Disjoint Networks (TDN)

© System-on-Chip Group, CSE-IMM, DTU 9 Conclusion Many NoC solutions exist, each attempting to combining different features The motivation of different architectures is the application on one side and technology on other side. The idea is to make the NoC application specific NoC, yet be general enough for reuse No one-fits-all NoC implementation is available though low power high speed solutions are desired

© System-on-Chip Group, CSE-IMM, DTU 10 References GUERRIER, P. and GREINER, A A generic architecture for on-chip packet- switched interconnections. In Design Automation and Test in Europe, DATE’00. DIELISSEN, J., RADULESCU, A., GOOSSENS, K., and RIJPKEMA, E Concepts and implementation of the phillips network-on-chip. In Proceedings of the IP based SOC IPSOC’03. BAINBRIDGE, J. and FURBER, S Chain: A delay-insensitive chip area interconnect. IEEE Micro. MILLBERG, M., NILSSON, E., THID, R., and JANTSCH, A Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip. In Proceedings of the conference on Design, automation and test in Europe. IEEE Computer Society. OSSO,M. D., BICCARI, G., GIOVANNINI, L., BERTOZZI, D., and BENINI, L ×pipes: a latency insensitive parameterized network-on-chip architecture for multi-processor socs. In Proceedings of 21st International Conference on Computer Design (ICCD04). IEEE Computer Society. JALABERT, A., MURALI, S., BENINI, L., and MICHELI, G. D ×pipesCompiler: A tool for instantiating application specific networks on chip. In Proceedings of Design, Automation and Testing in Europe Conference 2004 (DATE04). IEEE.