MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba MOSFET modeling for RF circuit design Nobuyuki Itoh Semiconductor Company Toshiba Corporation

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Recent Progress of MOSFET’s Performance CMOS VLSI Symp. 2004:f Tmax =209GHz (Intel) f Tmax =243GHz (IBM) SiGe Bipolar BCTM 2004:f Tmax =231GHz (Hitachi) f Tmax =230GHz (ST micro)

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Contents STI P-well S/D Diffusion Gate Gate Insulator N-well P-sub SiO 2  SiON Flicker Noise Increasing STI Stress For Small Geometry Device Thermal Noise Increasing due to Hot Carrier Scalable Substrate Network VTH based model or Surface potential model

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba VTH based model or Surface potential model STI P-well S/D Diffusion Gate Gate Insulator N-well P-sub VTH based model or Surface potential model

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Many Differences Two types of compact model VT-Based Model (BSIM, MM9 etc.) Surface Potential Model (HiSIM, EKV, MOS11 etc.) By Ref.[1]

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Difference btw simulation and measurement(1) Large (W/L=10/10) Short (W/L=10/0.14) BSIM4 EKV Discontinuous!! n-factor vs. V gs

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Difference btw simulation and measurement(2) Large (W/L=10/10) Short (W/L=10/0.14) BSIM4 EKV g m vs. I D

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Basic analog characteristics By Ref.[2]

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba VTH based model or Surface potential model Surface potential model seems better than VTH based model for analogue design. but… Surface potential model is not so popular right now

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Flicker noise STI P-well S/D Diffusion Gate Gate Insulator N-well P-sub SiO 2  SiON Flicker Noise Increasing

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Flicker Noise due to scaling Scaling  Thinner gate oxide  Gate leakage increasing  SiO2 to SiON  Flicker noise Thermal noise  RF performance degradation K F increasing Flicker noise degradation By Ref.[4]

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Cause of flicker noise degradation Nitrogen concentration [%] Depth [nm] Si substrateOxynitride 3.6X10 14 atoms/cm 2 1.6X X10 14 Pure Oxide N profile using NO annealing Pure Ox 3.6X10 14 atoms/cm 2 1.8X10 14 atoms/cm 2 Svg [V 2 - m 2 /Hz] Frequency [Hz] k10k N profile control is necessary! Peak N density was large influence of flicker noise Peak is in Si surface By Ref.[6]

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba N profile control N concentration [atm.%] depth [nm] oxynitride Si-sub. Vertical High Pressure (VHP) oxynitride process By Ref.[4] Remote-plasma nitridation By Ref.[5] 10 4 Frequency (H z ) Svg (V 2 -  m 2 /H z ) 10 1 NO anneal Nitrogen profile control By Ref.[7]

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Flicker noise Flicker noise is always problem in recent scaled MOSFET but… It seems not problem for its modeling

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba STI stress STI P-well S/D Diffusion Gate Gate Insulator N-well P-sub STI Stress For Small Geometry Device

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba STI Stress Low Stress High Stress Electron mobility degradation Hole mobility improvement Mechanical Stress By Ref.[8]

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba g m degradation due to STI stress Low stressed gate High stressed gate

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Inverter performance due to STI stress Mobility: large Capacitance: small Mobility: small Capacitance: large Mobility: small Capacitance: small Mobility: large Capacitance: large Stressed MOSFETStress-free MOSFET Which is better performance?

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba STI stress STI stress was modeled by BSIM4. but… It is not confirmed practical layout yet.

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Scalable substrate network STI P-well S/D Diffusion Gate Gate Insulator N-well P-sub Scalable Substrate Network

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Normal BCIM3 model s11 s21

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba MOSFET’s Equivalent Circuit for RF Gate Drain Source Sub Well BSIM3v3 model Cgb Rgb Rsjsub Rdjsub Rp Ddj Dsj Rg To realize scalable model, device geometry has to keep scalability By Ref.[3] Have to define target layout of MOEFET  R is defined by distance btw channel to contact

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Target Layout For Toshiba 0.13  m CMOS

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Scalable Model (L g dependence) s11 s22 s21 s12

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Scalable Model (W g dependence) s11 s22 s21 s12

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Scalable Model (V ds dependence) Vds=2.5V Vds=1.5V Vds=1.0V Vds=1.5V Vds=2.5V s11 s22 s21 s12

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Scalable Model (V gs dependence) Vgs=1.5V Vgs=1.2V Vgs=0.8V Vgs=1.2V Vgs=1.5V s11 s22 s21 s12

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Scalable substrate network Scalable substrate network was realized by in-house design tool. but… More accuracy and layout freedom is necessary

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Thermal noise STI P-well S/D Diffusion Gate Gate Insulator N-well P-sub Thermal Noise Increasing due to Hot Carrier

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Expressions Linear Region   =1   =1 Saturation Region   =0   =2/3 Classical model In the case of sub- micron MOSFET,  is increasing due to hot carrier effect! By Ref.[9] Recent model Philips 1999 Infineon 2001 By Ref.[10] By Ref.[11]

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba  vs. L g In the case of sub-0.1- micron MOSFET,  is larger than 4. 90nm  nm  6.1 in the estimation

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Noise measurement for Sub-0.1-micron NMOS Intrinsic device Tuner Network Analyzer Noise Source NF meter de-embeded capacitance by measurement gate resistance by calculation

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Measurement data NF50: -NF50 is decrease due to small gate length. -But it has bottom at around Lg=70nm. -It may  increasing dramatically

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Empirical formula Empirical equation

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Difference between this work and others

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba How affect to circuit performance estimation LNA  well known directly affect to circuit performance estimation VCO  Also affect to circuit performance estimation

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba VCO noise expression Generate

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Bipolar VCO Quit good correlation between measurement data and calculated data.. 1MHz offset

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Comparison of VCO noises Adapt  value which calculated by the empirical equation to several kinds of integrated MOSFET-VCO  =optimized: difference between measured and calculated is within +/- 2dB (average)  =0.67(fixed): difference between measured and calculated is large! Need suitable  value for thermal noise of MOSFET 1MHz offset

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Summary 1.Surface potential model seems better than V TH based model for analog circuit design due to its continuous characteristics. It needs entire discussion which model has to be chosen. 2.Scalable substrate network model has already been realized for limited layout. But it might be need more layout freedom. 3.Flicker noise increasing of SiON gate insulator is problems for performance. But accuracy of model is not issue. 4.STI stress model has been not popular, yet. We need more experience. 5.Thermal noise model is still issue.  is increasing due to scaling. It is the one of most important issues for RF analog designe.

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba Acknowledgments Great Tanks to; Dr. Sadayuki Yoshitomi Ms. Hisayo S. Momose Mr. Kenji Kojima Mr. Tatsuya Ohguro of Semiconductor Company, Toshiba Corporation

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba References [1]. R.van Langevelde, et, al., "RF Performance and Modeling of CMOS Devices," Educational Sessions Workbook of CICC, September, 2003 [2]. M.Bucher, "Analytical MOS Transistor Modeling for Analog Circuit Simulation," The Doctor Thesis of EPFL, pp.140, Lausanne, 2000 [3]. N.Itoh, et. al., "Scalable Parasitic Components Model of CMOS for RF Circuit Design," IEICE Transaction of Fundamentals, vol. E86-A, No.2, pp , February, [4]. H.Kimijima,et. al., "Improvement of 1/f noise by using VHP(Vertical High Pressure) oxynitride gate insulator for deep-sub micron RF and analog CMOS," Symp. VLSI Tech. Dig., pp , Kyoto, [5]. M. Rodder et., al, SSDM 1998 [6]. T.Ohguro, et. al., “The impact of oxynitride process, deuterium annealing and STI stress to 1/f noise of 0.11  m CMOS,” Symp. VLSI Tech. Dig., [7]. T.Ohguro, et. al., “A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides,” Symp. VLSI Tech. Dig., [8]. R.A.Bianchi, et. al., “Accurate Modeling of Trench Isolation Induced Mechanical Stress effects on MOSFET Electrical performance,” Proceedings of IEDM, [9]. Y.P. Tsividis, “Operation and Modeling of the MOS Transistor,” NewYork:McGraw-Hill, [10]. A.J.Scholten, et. al., “Accurate Thermal Noise Modeling for Deep-Submicron CMOS,” Proceedings of IEDM, [11]. G. Knoblinger, et. al., “A New Model for Thermal Channel Noise of Deep-Submicron MOSFETS and its Application in RF-CMOS Design,” IEEE Journal of Solid-State Circuits, vol.36, No.5, pp , May, [12]. A.J.Scholten, et. al., “Compact modeling of drain and gate current for RF CMOS,” Proceedings of IEDM, pp , [13]. G. Knoblinger, et. al., “Thermal Channel Noise of Quarter and Sub-Quarter Micron NMOS FET’s,” Proceedings of ICMTS, pp95-98, [14]. A.A. Abidi, “High-frequency noise measurements on FETs with small dimensions,” IEEE Trans. Electron Devices, vol.ED-33, pp , Nov., 1986.