P09311: Interface for Multi-Purpose Driver/Data Acquisition System Adam Van FleetProject Leader, EE DAQ Hardware Development David HoweElectrical Engineer USB & DAQ Hardware Design Mike DoroskiComputer Engineer FPGA-VHDL Design Andrew WeidaComputer Engineer Bluetooth-VHDL & GUI Design TJ AntonoffComputer Engineer USB-VHDL Design Sponsor: Dr. Marcin Lukowiak Rochester Institute of Technology Department of Computer Engineering

Project Overview Main Goal: Investigate and implement a reliable FPGA interface, utilizing various communication channels, for the multi-purpose driver/data acquisition (DAQ) system designed in P Key high level customer needs / engineering specs: – Graphical User Interface (GUI) Utilizes Windows OS Displays Connection Status Displays Connection Speed – USB Communication Channel Mbps Transfer Rate 0% Data Transfer Loss – Bluetooth Comm. Channel kbps Transfer Rate 0% Data Transfer Loss – Meet all P08311 Design Req’s

Hardware Design Concept RS-232 (230 kbps xfer) RS-232 USB Parani ESD210SK Bluetooth Dev. Kit Digilent Spartan-3 Board USB Adapter Windows-Based PC P08311 DAQ Board 64-pin (3.84 Mbps xfer) ASIC or Robotics Input 12-pin (up to 8Mb/s xfer)

System Flow Diagram DAQFPGAPC `

System Architecture DAQ FPGA USB Data Routing Logic USB FIFO USB Cable Bluetooth Modules Rx Tx Rx Tx RS kbps Bluetooth Wireless Serial PC 3.84 Mbps USB 8 Mbps Input Conditioning Output Conditioning Output Subsystem Input Subsystem UART 3.84 Mbps Control Unit

Major Risk Assessment Risk: Possibility for data transmission bottlenecks at FPGA interfaces – Action: Calculation of data rates (min and max) to ensure proper data flow Risk: Interfacing FPGA to DAQ to ensure proper operation / data flow – Action: Preliminary testing of DAQ board, research into hardware connection

Current State of Design Customer needs are met with design System design and subsystems meet project specifications Status: – Mock-Up of GUI designed has been programmed in C# – UART for bluetooth has been programmed in VHDL with communication to FPGA validated – Initial coding of USB logic and FPGA control logic /buffers under way, verification pending

Future Project Milestones MSD I Week 11 Design Finalized / Initial Testing Plan Devised MSD II Week 1-3 – Basic System Implementation / Testing Completion of all VHDL programming for FPGA and subsystems Establish GUI connection to FPGA Full testing and analysis of system with base Bluetooth / USB configurations Week 4-7 – Project Exploration Develop system with multiple Bluetooth / USB devices System testing to determine optimum speed / configuration Weeks 8-9 Analyze finished product for functionality of all systems Prepare documentation / poster Weeks 10 Finalize documentation / poster Project wrap-up / Design Review