Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure credit card transaction using 3DES encryption using Kerberos-style authentication. Current Stage: Full Chip LVS 03/24/2004 Design Manager: Rebecca Miller

Current Status  Design Proposal (100% done)  Architecture Proposal (100% done)  Size Estimate and Floor Plan (100% done)  Full-chip Transistor-level Schematic (100% done)  Component Layout & Simulation (100% done) Basic components Basic components  To be done Layout of larger blocks Layout of larger blocks Component Simulation Component Simulation Full Chip Layout (100% done) Full Chip Layout (100% done) Spice simulation of the entire chip Spice simulation of the entire chip

Schematic Reverification

Final Schematic

LVS Output

Poly & Active

Metal 1

Metal 2

Metal 3

Metal 4

Final Layout Input Latch Initial Permutation Barrel Shifting Key Register Barrel Shifting Initial Permutation Final Permutation Key Register XOR Expand Permutation P Permutation S BOX ROM and Decoders Program Control Transistors: Area: 378.8μm x μm

Dimensions um x um = 138,943.8 um^ um x um = 138,943.8 um^2 Transistor Count = Transistor Count = Transistor Density = 0.1 Transistor Density = 0.1 Aspect Ratio = 1 : 1.03 Aspect Ratio = 1 : 1.03 Estimated Clock Speed = 200Mhz Estimated Clock Speed = 200Mhz

Questions ?