Finite State Machines Mano and Kime Sections 4-4, 4-5, 4-8

Canonical Sequential Network State Register Combinational Network x(t) s(t+1) s(t) z(t) clk init present state present input next state present output

Mealy Machine State Register C1 x(t) s(t+1) s(t) z(t) clk init present state present input next state C2

Moore Machine State Register C1 x(t) s(t+1) s(t) z(t) clk init present state present input next state C2

VHDL Canonical Sequential Network State Register Combinational Network x(t) s(t+1) s(t) z(t) clk init present state present input next state present output process(clk, init) process(present_state, x)

VHDL Mealy Machine State Register C1 x(t) s(t+1) s(t) z(t) clk init present state present input next state C2 process(clk, init) process(present_state, x)

VHDL Moore Machine State Register C1 x(t) s(t+1) s(t) z(t) clk init present state present input next state C2 process(present_state, x) process(present_state) process(clk, init)

Example Detect input sequence 1101 fsm din dout clk clr din dout

Easy Solution: Use Shift Register CLK DQ !QCLK DQ !QCLK DQ !QCLK DQ !Q CLK Q0Q1Q2Q dout din

More General: Use State Diagram Detect input sequence 1101 S0 0 S1 0 S11 0 S110 0 S CLR

fsm.vhd fsm din dout clk clr

fsm.vhd

fsmx.vhd fsm clk_pulse SW1 bn BTN4 LD1 LD8 din dout clr clk fsmx IBUFG clkdiv mclk

fsmx.vhd entity fsmx is port( mclk : in STD_LOGIC; bn : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(1 to 8); BTN4 : in STD_LOGIC; led: out std_logic; ldg : out STD_LOGIC; LD : out STD_LOGIC_VECTOR(1 to 8) ); end fsmx;

fsmx.vhd

component clk_pulse port( BTN4 : in std_logic; cclk : in std_logic; clr : in std_logic; clk : out std_logic); end component; signal clr, clk, cclk, bnbuf: std_logic; signal clkdiv: std_logic_vector(23 downto 0);

fsmx.vhd U0: clk_pulse port map (BTN4 => BTN4, cclk => cclk, clr =>clr, clk => clk); U1: fsm port map (clr =>clr, clk => clk, din => SW(1), dout => LD(8)); LD(1) <= SW(1);

Detect input sequence 1101