Giga-Scale System-On-A-Chip International Center on System-on-a-Chip (ICSOC) Jason Cong University of California, Los Angeles Tel: , (Other participants are listed inside)

Jason Cong2 Project Summary Develop new design methodology to enable efficient giga-scale integration for system-on-a-chip (SOC) designs Project includes three major components –SOC synthesis tools and methodologies –SOC verification, test, and diagnosis –SOC design driver

Jason Cong3 Current Research Team  US  UCLA: Jason Cong  UC Santa Barbara: Tim Cheng  Taiwan  NTHU: Shi-Yu Huang, Tingting Hwang, J. K. Lee, Youn-Long Lin, C. L. Liu, Cheng-Wen Wu, Allen Wu  NCTU: Jing-Yang Jou  China  Tsinghua Univ.: Jinian Bian, Xianlong Hong, Zeyi Wang, Hongxi Xue  Peking Univ.: Xu Cheng  Zhejiang Univ.: Xiaolang Yan  Several new faculty members in the 7 institutions  Guest members from National University of Singapore, Purdue Univ., UCLA (EE Dept), and UT Austin

Jason Cong4 Thrust 1 -- SOC Synthesis Environment/Methodology (Led by Jason Cong) Code Generation for Retargetable Compiler and Assembler Generator Design Spec VHDL/C Co-Simulation Design Partitioning DSP Synthesis and Optimization FPGA Synthesis and Technology Mapping ASIC Synthesis Interconnect-Driven High-level Synthesis Synthesis for IP Reuse Physical Synthesis for Full-Chip Assembly Embedded Processors DSPs Embedded FPGAs Customiz ed Logic

Jason Cong5 Highlights of Accomplishments Novel microarchitecture and system methodology for multi-cycle on-chip communication –ISPD’03, ICCAD’03, DAC’04, T-CAD Optimality study of large-scale circuit placement –ASPDAC’03, ISPD’03, ICCAD’03, T-CAD Floorplanning with interconnect planning –About 30 papers published in DAC, ICCAD, ISPD, ASPDAC, ISCAS and Transactions P/G Network Analysis & Optimization –ICCAD’01, T-CAD, ASPDAC’04 Parasitic R/L/C extraction –ASPDAC, ASICON and IEEE Transaction on MTT

Jason Cong6 Thrust 2 -- SOC Verification, Test, and Diagnosis (Led by Tim Cheng) Verification and Testing Enabling techniques for semi- formal functional verification Integrated framework for simulation, vector generation and model checking Testing and diagnosis for heterogeneous SOC Self-testing using on-chip programmable components Self-testing for on- chip analog/mixed- signal components New test techniques for deep-submicron embedded memories Scalable constraint- solving techniques Automatic/semi- automatic functional vector generation from HDL code

Jason Cong7 Highlight of Accomplishments Developed and released ATPG-based SAT solvers for circuits – DATE2003, DAC2003, ICCAD2003, HLDVT2003 and ASPDAC2004 A new Statistical Delay Testing and Diagnosis framework consisting of five major components –DAC’02, ICCAD’02, DATE’03, DAC’03 On-Chip Jitter Extraction for Bit-Error-Rate (BER) Testing of Multi-GHz Signal – ASPDAC2004 and DATE2004

Jason Cong8 Thrust 3 – Design Driver: Network Security Processor (Led by Prof. C. W. Wu & Xu Cheng) Applications: IPSec, SSL, VPN, etc. Functionalities: –Public key: RSA, ECC –Secret key: AES –Hashing (Message authentication): HMAC (SHA-1/MD5) –Truly random number generator (FIPS 140-1,140-2 compliant) Target technology: 0.18  m or below Clock rate: 200MHz or higher (internal) 32-bit data and instruction word 10Gbps (OC192) Power: 1 to 10mW/MHz at 3V (LP to HP) Die size: 50mm 2 On-chip bus: AMBA (Advanced Microcontroller Bus Architecture)

Jason Cong9 Highlights of Accomplishments Security processor – encryption module –Secret key encryption module Operations: –Matrix operations, manipulation –AES cryptography –32-bit external interface –58K gates –Over 200MHz clock –Throughput: 2Gbps –Support key length of 128/192/256 bits Microprocessor -- Unity Processor –Used in over 7,000 NetPCs

Jason Cong10 International Collaborations Joint NSF/NSC workshop in Aug on SOC (Hsin-Chu, Taiwan) Preparation Efforts –1 st team preparation meeting for the proposed center in Jan (Yokohama, Japan) –2 nd planning meeting held in April 2000 (Hawaii, US) –3 rd planning meeting in Aug (Chengde, China) –Proposal submitted to NSF in Aug and funded in Dec. 2000

Jason Cong11 Workshops 1.March 30-31, 2001 in Taipei, Taiwan. 2.June 23-24, 2001 in Los Angeles, USA 3.August 31-September 1, 2001 in HangZhou, China 4.March 28-29, 2002, National Tsing Hua University, Hsinchu, Taiwan 5.August 20-21, 2002, Peking University, Beijing, China 6.November 15-16, 2002, University of California, Santa Barbara 7.March 27-29, 2003, National Taiwan University, Taipei, Taiwan 8.December 19-21, 2003, Yunnan University, Kunming, China 9.August 6-8, 2004, Changsha, China 10.November 22-23, 2004, Oahu, Hawaii, USA

Jason Cong12 Publications 293 publications as of March publications involving both PIs from U.S

Jason Cong13 People & Education Many interactions among participants from different institutes Two new IEEE fellows: –Prof. Xiaolang Hong, Tsinghua Univ. –Prof. Cheng-Wen Wu, National Tsing Hua Univ. Involved many young faculty members and researchers Trained an army of graduate students