Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM Test Set Compaction for Sequential Circuits based on Test Relaxation M.S Thesis Defense S. Saqib Khursheed Advisor: Dr. Aiman H. El-Maleh Members: Dr. Sadiq M. Sait & Dr. Alaaeldin Amin 29 th Dec 04

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 2 Motivation State of the Art Static Compaction Algorithms Test Relaxation Algorithm Proposed Algorithms and Experimental Results Limitations of Justification algorithm Conclusion & Future Work Outline

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 3 Motivation Compaction is the process of reducing the size of test set while maintaining the fault-coverage. To overcome High Complexity of Sequential ATPGs To reduce Test Application Time  reduced cost! To overcome Memory Limitations of the Tester.

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 4 Static Compaction  Compaction Algorithms are applied as a post-processing step to test generation process. Dynamic Compaction  Compaction Algorithms are incorporated in test generation process. Static Compaction is more useful than Dynamic Compaction in Sequential Circuits. Types of Compaction Algorithms

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 5 Some of the popular algorithms include: –Vector Restoration Linear Reverse Order Restoration (LROR) Radix Reverse Order Restoration (RROR) SIngle FAult Restoration (SIFAR) Mixed Mode (MISC) SECO –Subsequence Merging –State Traversal based on Relaxed States State-of-the-art Static Compaction Algorithms

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 6 LROR Snapshot of algorithm under execution Targeting f 1 and f 2. Restoring vector #6 doesn’t detect the fault Targeting f 1 and f 2. Restoring vector # 5 and 6, doesn’t detect the faults Restoring vector # 4, 5 and 6, detects the fault f 1 and f 2. f 1 and f 2 detected Restored vector # 4, 5 and 6, are concatenated with previously restored test vectors.

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 7 State-Traversal

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 8 Important Attributes of Static Compaction Algorithms Test sequences for Hard-to-Detect faults (HTDF) can easily detect Easy-to-Detect faults (ETDF). State Traversal eliminates redundant vectors Merging of relaxed Subsequences adds another level of freedom to test compaction. Increasing the Fault coverage fuels compaction.

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 9 Restoration algorithms rely on vector-by-vector fault simulation to extract the test sequence. Recently, an efficient Test Relaxation technique has been proposed to extract the necessary assignments for detecting the faults. Our algorithms (discussed next) rely on test relaxation algorithm for extracting the self-initializing subsequence. A relaxed test set facilitates Subsequence Merging and State Traversal. Test Relaxation Algorithm

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 10 Proposed Algorithms Following algorithms are proposed: –Linear Reverse Order Restoration with State Traversal with State Traversal-2 –Merging Restoration –Hybrid Schemes Hybrid-I Hybrid-II –Fault-Coverage based Compaction FC-LROR FC-MR

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 11 Reverse Order Restoration with State Traversal using Relaxed Test Set After first pass of fault simulation, information is stored Justification of faults f 4, f 5. Self-initialized subsequence is found by relaxation algorithm. f 4 and f 5 detected State Traversal may further reduce the size of subsequence Re-current states, removal of time frames is possible f 4 and f 5 detected Start from last time frame having un-justified fault. f 4 and f 5 detected Reduced subsequence

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 12 Reverse Order Restoration with State Traversal using Relaxed Test Set Fault Simulate the subsequence and drop all the faults detected f 4, f 5, f 1 and f 2 are detected Dropping detected faults leaves f 3 The above steps are repeated Fault # 3 is justified. Concatenation with previously justified test vectors. Test Set after Compaction detecting all the faults. 0/1 1/x 1/0 0/x 1/x x/0

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 13 Motivation behind ST-2 STRATEGATE Test Sequences LRORLROR-ST CktTSTS (sec) s (0.06)134 (0.06) s (0.03)44 (0.09) s (0.07)157 (0.11) s (0.07)134 (0.1) s (0.27)466 (0.39) s (0.31)470 (0.42) s (0.3)268 (0.35) s (0.33)268 (0.37) s (0.56)479 (0.71) s (0.52)401 (0.7) s (45.34)726 (45.34) s (20.8)131 (21.12) Total (sec) (68.66)3678 (69.76)

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 14 Merging algorithm follows the same flow as the previous algorithm. Instead of concatenation of subsequences, relaxed subsequences are merged with previously restored subsequences. Merging towards bottom Merging towards top Merging Restoration

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 15 11xx 0x01 10x1 xxx0 00x1 11xx x0 001x Compact Test Set Newly Restored Subsequence X X 11xx 0x x xx Merged Subsequence Merging towards Bottom

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 16 Exp. Results STRATEGATE Test Sequences ITE LROR [14]MRLRORLROR-STLROR_ST2LROR [14]LROR_ST2 CktTSTS (sec) s (0.14)154 (0.05)152 (0.09)134 (0.06)152 (0.11)112 (0.74)152 (0.15) s (0.09)61 (0.04)44 (0.1)44 (0.09)44(0.1)51 (0.18)44 (0.13) s (0.13)148 (0.59)133 (0.07)157 (0.11)119 (0.17)117 (0.32)118 (0.56) s (0.16)140 (0.54)115 (0.07)134 (0.1)112 (0.25)103 (0.61)111 (0.49) s (0.79)531 (3.11)469 (0.64)466 (0.39)456 (0.59)471 (1.94)428 (1.96) s (0.89)568 (3.31)534 (0.45)470 (0.42)498 (0.6)443 (4.5)460 (2.28) s (0.28)242 (1.79)268 (0.59)268 (0.35)268 (1.17)260 (1.2)266 (1.21) s (0.31)248 (2.18)268 (0.62)268 (0.37)268 (1.23)270 (1.09)266 (1.64) s (1.79)533 (5.38)466 (0.56)479 (0.71)453 (1.01)474 (14.89)423 (4.0) s (1.71)501 (4.82)453 (0.67)401 (0.7)434 (0.88)422 (21.92)434 (2.39) s (38.71)1549 (227.57)760 (45.34)726 (45.34)710 (51.8)585 (71.55)703 (74.46) s (56.93)188 (389.7)131 (20.8)131 (21.12)131 (22.5)137 (119.76)125 (128.66) Total (sec) (101.9)4863 (639.1)3793 (68.66)3678 (69.76)3645 (80.41)3445 (238.7)3530 (217.95) Better

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 17 Merging Restoration Number of SS restored MRLROR-ST2 Ckts# of SS s29886 s s s s s s s s s s s Total

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 18 Hybrid Schemes LROR suffers from quick saturation. Hybrid schemes are proposed to address this limitation of LROR. Hybrid-I uses Test Relaxation and random filling to change the composition of the test. This helps moving the algorithm out of local-minima and search space is therefore increased.

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 19 Hybrid Schemes LROR-ST2 2+ Test Relaxation 3+ Hybrid-I

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 20 Hybrid Schemes Hybrid-I Hybrid-II MR 1+

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 21 Hybrid Schemes STRATEGATE Test Sequences ITE LROR [12]SIFAR [13]MISC [12]Hyb-IHyb-II CktTSTS (sec) s (0.6)112 (0.4)98 (3.2)106 (0.96)89 (1.16) s (0.1)48 (0.2)43 (0.4)48 (0.26)48 (0.31) s (0.5)87 (0.4)63 (1.7)68 (1.48)68 (1.64) s (0.6)94 (1.1)60 (0.8)64 (1.37)64 (1.54) s (6.4)388 (6.5)335 (15.2)377 (18.1)376 (22) s (8.8)435 (4.5)368 (14.0)418 (18.9)406 (24.3) s (1.7)237 (3.4)216 (3.2)213 (37.4)182 (41.5) s (2.6)251 (1.5)222 (3.6)222 (33.1)196 (36.6) s (27.1)312 (8.8)364 (39.4)362 (17.4)361 (24.5) s (339.4)597 (89.5)583 (2148)637 (307.4)637 (383.7) s (752.3)152 (290)101 (1177)133 (875.76)133 (1002.7) Total (sec) (1140.1)2713 (406.3)2453 (3406.5)2648 (1326.6)2560 (1539.9) Better Equal

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 22 HITEC Test Sequences ITE LROR [12]MISC [12]Hyb-IHyb-II CktTSTS (sec) s (0.8)97 (1.1)161 (0.87)143 (0.98) s (0.1)47 (0.5)45 (0.5)45 (0.53) s (1.0)72 (1.2)66 (2.15)66 (2.28) s (0.7)74 (1.0)71 (1.6)71 (1.77) s (13.8)432 (28.3)489 (24)488 (27.4) s (8.3)383 (64.0)497 (17.7)493 (20.5) s (2.3)223 (2.5)214 (35.6)187 (38.8) s (1.9)225 (1.9)218 (42.7)184 (51.8) s (10.4)572 (354.6)650 (40.4)648 (49.6) s (108.1)271 (189.0)262 (90.8)262 (107.3) s (227.8)117 (1158)187 (1020.8)145 (1379.6) s (24.6)443 (265.0)682 (54.6)369 (103.2) s (11.6)92 (13.1)104 (17.3)75 (20.1) s (20.5)315 (25.6)272 (379.8)133 (430.1) Total (sec) (431.9)3363 (2105.8)3918 (1728.9)3309 (2233.6) Hybrid Schemes Better Equal

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 23 Motivation: A large reduction in test size is possible by increasing the fault coverage of currently restored subsequences. This is achieved by relaxing and randomly filling the restored SS. Fault coverage (FC) based compaction: –LROR based on increasing the FC  FC-LROR –MR based on increasing the FC  FC-MR Fault-Coverage based Compaction

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 24 Fault-Coverage based Compaction IDEA LROR FC-LROR

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 25 FC-LROR Currently Compacted Test New SS Test Relaxation Yes End No Und Faults? n

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 26 FC-MR Fully Specified New SS Random Filling & Test Relaxation Yes End No Und Faults? n Test Relaxation for all und. faults Merging towards Top Currently Compacted Test

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 27 Exp. Results: FC-based Compaction HITEC Test Sequences CktTSSECO [37]SIFAR [13]LROR [12]FC-LRORMRFC-MRMISC [12] s s s s s s s s s s s Total Better Equal All

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 28 Exp. Results: FC-based Compaction STRATEGATE Test Sequences CktTSLROR [14]SIFAR [13]LROR [12]MRFC-MRFC-LRORMISC [12] s s s s s s s s s s s Total Better All

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 29 Hybrid-FC-LROR FC-LROR MR 1+ 2+

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 30 Exp. Results: Hybrid-FC-LROR STRATEGATE Test Sequences CircuitTS ITE LROR [12] ITE SIFAR [13] ITE MISC[12] ITE Hyb-FC-LROR S S S S S S S S S S S Total Better

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 31 Exp. Results: Hybrid-FC-LROR HITEC Test Sequences ITE CktTSLROR [12]MISC [12]Hyb-FC-LROR s s s s s s s s s s s s s s s Total

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 32 Limitations of Justification Algorithm Justification of G/F value is done based on cost functions, which is an approximate method. Cost of Good value is only used. These limitations result in extraction of longer test sequences than necessary.

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 33 Conclusion & Future Work In this work, we have proposed several efficient static compaction techniques, which achieve the following: –Better or comparable level of compaction while reducing the runtime. –All important attributes of static compaction techniques are integrated. –Limitation of quick saturation of Restoration based techniques has been addressed. –A new class of compaction algorithms has been introduced, based on increasing the fault-coverage of restored subsequences.

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 34 Conclusion & Future Work Investigate techniques to overcome the limitations of Justification Algorithm. Investigate techniques for increasing the fault coverage of an extracted Subsequences.

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 35 Thank you! Q & A

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 36 Backup Slides

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 37 Unique opportunities provided by Static Compaction: –It may be applied to test vectors generated by any ATPG tool without modifying the test generation process. –It may be applied after dynamic compaction. –It takes lesser time to get final test set. –The shortest test sequence for sequential circuits are generated by static compaction techniques. For these reasons, Static Compaction is more popular in Sequential circuits than Dynamic Compaction. Types of Compaction Algorithms

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 38 Modified LROR

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 39 SIFAR uses the basic idea of Test Vector Restoration. It considers a single target fault (in decreasing order of detection time) and restores test vectors until fault is detected. –This is also called Test Vector Restoration. SIFAR uses parallel fault simulator to speed up the restoration process. State-of-the-art Static Compaction Algorithms (SIFAR)

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 40 SIFAR Targeting f 1. Restoring vector #6 doesn’t detect the fault Targeting f 1. Restoring vector # 5 and 6, doesn’t detect the fault Restoring vector # 4, 5 and 6, detects the fault f 1. F 1 detected Restored vector # 4, 5 and 6, are concatenated with previously restored test vectors. Snapshot of algorithm under execution

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 41 RROR is a variation of LROR, meant to speed up the restoration process. In RROR, rather than restoring frame by frame, the algorithm jumps to previous time frames. Radix Search is based on binary search and depends on the value of r i-1, such that, 1< r ≤ 2 and i=1,2,3.. The algorithm keeps jumping until the target fault(s) is detected. State-of-the-art Static Compaction Algorithms (RROR)

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 42 RROR Snapshot of algorithm under execution Targeting f 1 and f 2. Restoring vector #9 doesn’t detect the fault. r=2, i=1 Restoring vector # 7, 8 and 9, doesn’t detect the fault f 1 and f 2. r=2, i=2 f 1 and f 2 detected Restoring vector # 3, 4, 5 and 6, detects the faults f 1 and f 2. r=2, i=3 Restored vector # 3, 4 … 9, are concatenated with previously restored test vectors.

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 43 A newly restored subsequence may be merged with previous subsequences either towards Top or Bottom or from where the savings are highest. Merging towards bottom  starts from top and slides the newly restored SS downwards until merged or appended. Merging towards TOP  starts from Bottom and slides the newly restored SS upwards until merged or appended Merging Restoration

Test Set Compaction for Sequential Circuits Computer Engineering, KFUPM 44 Fault-Coverage based Compaction Observations: Initially restored test sequences cover a large number of faults. This is called covering effect, which is used by Restoration based compaction algorithms. Motivation: A large reduction in test size is possible by increasing the fault coverage of currently restored subsequences.