A Multi Gigabit FPGA-based 5-tuple classification system Author: Antonis Nikitakis, Ioannis Papaefstathiou; Publisher: Communications, ICC '08. IEEE International Conference on Presenter: Yu-Ping Chiang Date: 2008/10/15

Outline 2sBFCE Architecture  Overview  Single Field Operations  Permutation Engine  Bloom Filter (2nd stage)  Rule Table Simulation Result

Outline 2sBFCE Architecture  Overview  Single Field Operations  Permutation Engine  Bloom Filter (2nd stage)  Rule Table Simulation Result

Single Field Matching Two Bloom Filters used in Src IP / Dest IP field  For most common lengths (16, 24, 32).  For other lengths. →Complete stage1 in 17 clock cycles. One Bloom Filter used in other field.

Single Field Matching Internal representation: IP field + length  SourceIP / DestIP: 32+6 bits  Source-Port/Dest-Port: 16+5 bits  Protocol: 2 bits →120-bit rule vector (use by hash function as input)

Permutation Engine.  #Src IP / #Dest IP = 33  #Src Port / #Dest IP = 17  #Protocol = 2 (deal at last stage) Usually less than 5 match in each field.

Bloom Filter Two hashing function  2 bits access, 2 memory access. →dual port memory module Hash function . q(i) = derives from randomized vector x(i) = rule vector

Bloom Filter False positive Don’t support incremental updates. One memory access each permutation.  Avg clock cycles

Rules Table Keep whole information of rule and FlowID  If match, output FlowID.. 12-bit FlowID (4K rules) Set priority for finding best one.

Rules Table Hash indexing  Variable size blocks holding colliding FlowIDs. → search sequentially. Deal protocol field

Outline 2sBFCE Architecture  Overview  First Stage Single Field Operations Permutation Engine  Second Stage Bloom Filter Rule Table Simulation Result

Results Memory requierment:  Single field & second stage: 178 KB Query time:  Primary design: avg. 42 clock cycles/query 42 * 6.56ns = ns/packet 3.63 Mpps (MegaPacketsPerSecond)  Improved design: avg. 26 clock cycles/query 26 * 6.56ns = ns/packet 5.86 Mpps

Results