Midterm Tuesday October 23 Covers Chapters 3 through 6 - Buses, Clocks, Timing, Edge Triggering, Level Triggering - Cache Memory Systems - Internal Memory – RAM & DRAMS Systems, Data Transfer Timing, Coding - External memory – Magnetic Disks, RAID, Optical Memory Study Homework, Lecture Slides, Text

Chapter 7 Input/Output

Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower than CPU and RAM Need I/O Interfaces (modules) or channels

Generic Model of I/O Module

I/O Module Function Support single or multiple devices Hide or reveal device properties Provides: Control & Timing CPU Communication Device Communication Data Buffering Error Detection

I/O Module Diagram

Input Output Techniques Programmed Interrupt driven Direct Memory Access (DMA)

Programmed I/O CPU has direct control over I/O —Sensing status —Read/write commands —Transferring data CPU waits for I/O module to complete operation Usually not a good use of CPU time

Programmed I/O - detail CPU requests I/O operation I/O module performs operation I/O module sets status bits While CPU checks status bits periodically CPU may wait or come back later

Interrupt driven I/O - CPU Viewpoint Issue I/O command Do other work - Check for interrupt at end of each instruction cycle When interrupt is requested AND request is granted —Save context (registers: data & control) —Process interrupt –Execute “service routine” Continue other work

Interrupt Driven I/O – Device Perspective CPU issues I/O command (including enable interrupt) I/O module gets/puts data from/to peripheral while CPU does other work I/O module interrupts CPU (Interrupt request) Device serviced by CPU

Interrupt Physical Model CPU —General Purpose Registers –Program counter (PC) –Stack Pointer (SP) +User stack Pointer Storage +Supervisor Stack Pointer Storage —Program Status Word (PSW) – Includes –State – user/supervisor, priority, etc. –Program Priority –Condition Codes (CC) —Hardware to communicate over the BUS –Address, Data, and Data Control –Bus status and control Memory —User program —Interrupt Service Routine —Operating System —Interrupt Vector Table –Includes an entry that points to the Interrupt Service Routine (Interrupt vector #) Device —Status/Control Register(s) – Includes: –Interrupt Enable bit –Interrupt bit (sometimes called ready or done) —Priority Level for Interrupt Service Routine (In hardware or firmware) —Interrupt vector number (In hardware or firmware) —Hardware to communicate with CPU over the BUS

Interrupt Sequence 1)What does the programmer do? 2)What does the computer do?

Interrupt Sequence 1)Programmer Action: Enable Interrupts by setting “intr enable” bit in Device Status Reg 2)Enabling Mechanism for device: When device wants service, and its enable bit is set (,i.e, the I/O device has the right to request service), and its priority is higher than the priority of the presently running program, and execution of an instruction is complete, then the processor initiates the interrupt 4)Process to Service the Interrupt: The Processor saves the “state” of the program (has to be able to return) The Processor goes into Privileged or Supervisor Mode The Priority level is set (established by the interrupting device) The user SP is saved and the Supervisor SP loaded The (PC) and the (PSR) are PUSHED onto the Supervisor Stack The contents of the other registers are not saved. Why? The CC’s are cleared 5)The Processor Loads the PC from the Interrupt Vector Table 6)Interrupt Service Routine is executed It ends with an RTI 7)The stored user PSR (POP into PSR), PC (POP into PC), USP loaded And the next instruction fetched