University of Toronto Pre-Layout Estimation of Individual Wire Lengths Srinivas Bodapati (Univ. of Illinois) Farid N. Najm (Univ. of Toronto)

SLIP 2000Bodapati & Najm2 Introduction n Interconnect represents an increasingly significant part of total circuit delay l Longer interconnect is more significant n Interconnect is accurately known only after place/route l This leads to timing closure problems l Logic design is now coupled with physical design n Interconnect must be considered during: l Floorplanning, synthesis, timing verification n We need to be able to predict the length of individual wires before layout, say during technology mapping n Traditional wire load models give only average load

SLIP 2000Bodapati & Najm3 Wire Load Models not Enough (Source: Kapadia & Horowitz, DAC-99)

SLIP 2000Bodapati & Najm4 Previous Work n Previous work in this area: l Pedram and Preas, ICCD-89 u Average wire length for given pin-count l Heineken and Maly, CICC-96 u Wire-length distribution l Hamada, Cheng, and Chau, TCAD 8/96 u Average wire length for given pin-count l Others … n Previous work has focused on aggregate metrics (average, distribution) n Given the spread in wire-length values, individual wire length estimation is required

SLIP 2000Bodapati & Najm5 Alternative n Traditional wireload models are failing: l They only predict average net behavior l They only predict wire capacitance, not length or resistance u Resistive shielding is important in DSM n We are developing wire length predictors (for individual wires or nets) that work at the netlist level, pre-layout n A black-box model is built using linear regression on a number of variables: l Base-length, expressed a function of the pin-count of a net l Various congestion metrics, expressed as functions of a number of local and global primitive variables n Technique verified using Cadence’s Silicon Ensemble

SLIP 2000Bodapati & Najm6 Proposed Model Structure n General features of the model: l Short wires (less than 70 um) are excluded, due to noise l Mid-range wires are estimated via a regression model, built by a one- time up-front characterization process l Long wires (more than 7 pins) are handled via bounding box method

SLIP 2000Bodapati & Najm7 Basic Parameters - Local n Local parameters capture significant attributes of individual nets and of the net neighborhood n The number of pins on a net (denoted P net ) is known to affect net length: n We use P net as a key local parameter n Other local parameters are defined based on the notion of a neighborhood (data from the characterization set, table 4.1)

SLIP 2000Bodapati & Najm8 Neighborhood - First Level n The first level neighborhood (denoted N h1 (i) ) of a given net i is defined as: l The set of all other nets connected to cells to which this net is also connected n In this figure, N h1 (10) = { 6, 7, 9, 11, 8, 12, 13 }

SLIP 2000Bodapati & Najm9 Neighborhood - Second Level n The second level neighborhood (denoted N h2 (i) ) of a given net i is defined as: l The union of all first level neighborhoods of nets that are in the first level neighborhood of this net n In this figure, N h2 (10) = { 1, 2, 5, 11, 9, 14, 3, 4, 12, 13, 8, 15, 16 }

SLIP 2000Bodapati & Najm10 Neighborhood n The neighborhood of a net is defined as the union of its first and second level neighborhoods n The neighborhood of net 10 is shown: n With this, define other local parameters (k = 2, 3, 4, 5, 6) : l N knet is number of nets in the neighborhood that have k pins

SLIP 2000Bodapati & Najm11 Basic Parameters - Global n Global parameters capture significant global attributes of the design: l Number of cells in the design, N c l For k = 2, 3, 4, 5, 6, number of k-pin nets in the design, N kagg u This is also the number of gates with k-pin nets at their output l Average cell width in this design, W avg n Other global parameters are specified as parameters to be used by the layout engine: l Aspect ratio, R l Row utilization factor, U n In our work, R = 1 and U = 85% were kept constant

SLIP 2000Bodapati & Najm12 Intermediate Variables n Intermediate variables are defined based on the basic parameters, and include: l Base length, L nbase l Congestion metrics, P kcon, k = 2, 3, 4, 5, 6, and N 2oth, N 3oth n Base length is defined based on P net, as the average of: l The net length if all cells on the net are placed in vertical stack l The net length if all cells on the net are placed in horizontal row l Thus: where H cell is the height of a cell (in our case um)

SLIP 2000Bodapati & Najm13 Base Length is Important (data from the characterization set, table 4.1, excluding short wires)

SLIP 2000Bodapati & Najm14 Low Pin-Count Nets Placed First n An observed key feature of Silicon Ensemble is that low pin-count nets (2, 3 pins) are placed first n Since these represent a large fraction of the total, this approach leads to a smaller overall net length n Consequences of this: l 2 or 3 pin nets are placed very close together, because very little else has been placed by then, hence limited relative placements l low pin-count nets are spread out on the layout surface irrespective of their impact on higher pin-count nets l low pin-count nets become the main obstacles to routing higher pin-count nets - they cause congestion n This motivates our definition of congestion metrics

SLIP 2000Bodapati & Najm15 Congestion Metrics n A high pin-count net would be long if: l It has a large number of low pin-count nets in its neighborhood l These low pin-count nets are spread out over a large layout area n Focusing on 2-pin nets in the neighborhood, we capture the above with the following 2-pin congestion metric: n The term on the right is a measure of the number of possible ways and locations of placing a 2-pin net n Likewise, we define P 3con, P 4con, P 5con, and P 6con

SLIP 2000Bodapati & Najm16 Net Length v.s. P 2con (data from the characterization set, table 4.1, excluding short wires)

SLIP 2000Bodapati & Najm17 One more Congestion Metric n The above metrics capture congestion and spread due to low pin-count nets that belong to the neighborhood n Other low pin-count nets, that do not belong to the neighborhood, can also impact net length, if: l A large number of them are placed in the same general layout area that the net neighborhood will occupy l These nets can become obstacles … they are in the way n For 2-pin nets, we capture this with the following: n Likewise, we define N 3oth as the last congestion metric

SLIP 2000Bodapati & Najm18 Net Length v.s. N 2oth (data from the characterization set, table 4.1, excluding short wires)

SLIP 2000Bodapati & Najm19 The Polynomial Model n With all the above variables, we express net length as: where f(.) is a polynomial template (quadratic or cubic is enough) n The polynomial coefficients are computed by linear regression, based on a set of benchmark circuits l We call these the characterization circuits (see next slide) n The technique was then tested on a different set of circuits l We call these the test circuits (shown later on) n Before showing the results, we will discuss the special case treatment for very short and very long wires

SLIP 2000Bodapati & Najm20 The Characterization Circuits (ISCAS and MCNC benchmark circuits)

SLIP 2000Bodapati & Najm21 Special Case: Short Wires n Length of short wires (less than about 70 um) was found to be very sensitive to various insignificant parameters: l Cell names, net names, order in which cells are listed n The circuit is alu2o (368 gates, 380 nets) n All that was varied in this case was the cell names in the netlist

SLIP 2000Bodapati & Najm22 Special Case: Short Wires n This is probably due to the heuristic nature of the tools n This does not represent a problem with the P&R tool l Total net length is typically used as an objective function l Multiple layout solutions can have similar total net length n For purposes of individual net length estimation, these variations represent “noise,” which can be a problem l The noise is there for longer wires as well, but is not as bad (as we’ll see later); luckily, we are less concerned about short wires n Consequences: l Estimation of short wires is practically impossible l Individual wire length estimation cannot be done beyond a certain accuracy level; this “noise floor” depends on the tool

SLIP 2000Bodapati & Najm23 Special Case: Long Wires n For nets with more than 7 pins, special case treatment was found to be required n Since these nets are routed “last”, then: l Their placement options become restricted, and l Their large neighborhoods are spread out n To handle these nets, we use a method based on the commonly used concept of a bounding box l Box area is estimated from intermediate variables l Box height is computed assuming each cell in different row l Use either result from Caldwell et al. or half-perimeter as the estimate of net length

SLIP 2000Bodapati & Najm24 Experimental Results n Implementation: l ISCAS, MCNC circuits were optimized and mapped using SIS l Place & route was done with Cadence’ Silicon Ensemble l Library: u 102 cells u 1.40 um (metal pitch) u 4 metal layers u cell height is um u core site width is 1.40 um n Characterization was done using the characterization circuits (shown previously) n Testing was done with the test circuits (see next slide)

SLIP 2000Bodapati & Najm25 The Test Circuits (ISCAS and MCNC benchmark circuits)

SLIP 2000Bodapati & Najm26 Results and Noise alu2o alu2o noise s1238o s1238o noise

SLIP 2000Bodapati & Najm27 Results and Noise apex6oapex6o noise frg2o frg2o noise

SLIP 2000Bodapati & Najm28 Results and Noise x3ox3o noise random10random10 noise

SLIP 2000Bodapati & Najm29 Long Wires - Results (data from all the test circuits)

SLIP 2000Bodapati & Najm30 Long Wires - Noise (data from all the test circuits)

SLIP 2000Bodapati & Najm31 Total Average Error (long wires data is from all the test circuits)

SLIP 2000Bodapati & Najm32 Summary & Conclusion n Problem: l Interconnect can no longer be ignored l Wire load models are no longer good enough l Need prediction of individual wire lengths before layout n Proposed solution: l Black box model of net length based on various metrics that are extracted from the netlist - regression on polynomial template l Short wires excluded - due to noise l Long wires handled as special case - bounding box approach n Unavoidable noise is due to heuristics in P&R tools n Individual net length estimation is possible, within the limits due to this noise