1 Evgeny Bolotin – ClubNet Nov 2003 Network on Chip (NoC) Evgeny Bolotin Supervisors: Israel Cidon, Ran Ginosar and Avinoam Kolodny ClubNet - November.

Slides:



Advertisements
Similar presentations
Best of Both Worlds: A Bus-Enhanced Network on-Chip (BENoC) Ran Manevich, Isask har (Zigi) Walter, Israel Cidon, and Avinoam Kolodny Technion – Israel.
Advertisements

Evaluation of On-Chip Interconnect Architectures for Multi-Core DSP Students : Haim Assor, Horesh Ben Shitrit 2. Shared Bus 3. Fabric 4. Network on Chip.
A Novel 3D Layer-Multiplexed On-Chip Network
Presentation of Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip by Christian Neeb and Norbert Wehn and Workload Driven Synthesis.
REAL-TIME COMMUNICATION ANALYSIS FOR NOCS WITH WORMHOLE SWITCHING Presented by Sina Gholamian, 1 09/11/2011.
Handling Global Traffic in Future CMP NoCs Ran Manevich, Israel Cidon, and Avinoam Kolodny. Group Research QNoC Electrical Engineering Department Technion.
1 Asynchronous Bit-stream Compression (ABC) IEEE 2006 ABC Asynchronous Bit-stream Compression Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar Technion.
Technion – Israel Institute of Technology Qualcomm Corp. Research and Development, San Diego, California Leveraging Application-Level Requirements in the.
Module R R RRR R RRRRR RR R R R R Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip Zvika Guz, Isask ’ har Walter, Evgeny Bolotin, Israel.
NETWORK ON CHIP ROUTER Students : Itzik Ben - shushan Jonathan Silber Instructor : Isaschar Walter Final presentation part A Winter 2006.
Department of Computer Engineering University of California at Santa Cruz Networking Systems (1) Hai Tao.
1 Evgeny Bolotin – Efficient Routing, DATE 2007 Routing Table Minimization for Irregular Mesh NoCs Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny.
Network based System on Chip Performed by: Medvedev Alexey Supervisor: Walter Isaschar (Zigmond) Winter-Spring 2006.
MICRO-MODEM RELIABILITY SOLUTION FOR NOC COMMUNICATIONS Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar Technion – Israel.
LOW-LEAKAGE REPEATERS FOR NETWORK-ON-CHIP INTERCONNECTS Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar Technion – Israel Institute of.
NoC: Network OR Chip? Israel Cidon Technion. Israel Cidon, Technion Technion’s NoC Research: PIs  Israel Cidon (networking)  Ran Ginosar (VLSI)  Idit.
GeNoLator – Generic Network Simulator Final Presentation Students: Gal Ben-Haim, Dan Blechner Supervisor: Isask'har Walter Winter 08/09 18/08/2009.
1 Multi - Core fast Communication for SoPC Multi - Core fast Communication for SoPC Technion – Israel Institute of Technology Department of Electrical.
1 Link Division Multiplexing (LDM) for NoC Links IEEE 2006 LDM Link Division Multiplexing Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar Technion –
1 E. Bolotin – The Power of Priority, NoCs 2007 The Power of Priority : NoC based Distributed Cache Coherency Evgeny Bolotin, Zvika Guz, Israel Cidon,
1 1 Networks on Chips (NoC) – Keeping up with Rent’s Rule and Moore’s Law Avi Kolodny Technion – Israel Institute of Technology International Workshop.
1 Evgeny Bolotin – ICECS 2004 Automatic Hardware-Efficient SoC Integration by QoS Network on Chip Electrical Engineering Department, Technion, Haifa, Israel.
Architecture and Routing for NoC-based FPGA Israel Cidon* *joint work with Roman Gindin and Idit Keidar.
Statistical Approach to NoC Design Itamar Cohen, Ori Rottenstreich and Isaac Keslassy Technion (Israel)
CPU Chips The logical pinout of a generic CPU. The arrows indicate input signals and output signals. The short diagonal lines indicate that multiple pins.
Network-on-Chip: Communication Synthesis Department of Computer Science Texas A&M University.
Storage area network and System area network (SAN)
Dragonfly Topology and Routing
Mohamed ABDELFATTAH Vaughn BETZ. 2 Why NoCs on FPGAs? Embedded NoCs Area & Power Analysis Comparison Against P2P/Buses 4 4.
Performance and Power Efficient On-Chip Communication Using Adaptive Virtual Point-to-Point Connections M. Modarressi, H. Sarbazi-Azad, and A. Tavakkol.
High Performance Embedded Computing © 2007 Elsevier Lecture 16: Interconnection Networks Embedded Computing Systems Mikko Lipasti, adapted from M. Schulte.
Chapter 6 High-Speed LANs Chapter 6 High-Speed LANs.
NETWORK-ON-CHIP (NOC): A New SoC Paradigm
LECTURE 9 CT1303 LAN. LAN DEVICES Network: Nodes: Service units: PC Interface processing Modules: it doesn’t generate data, but just it process it and.
Communication issues for NOC By Farhadur Arifin. Objective: Future system of NOC will have strong requirment on reusability and communication performance.
On-Chip Networks and Testing
Introduction to Interconnection Networks. Introduction to Interconnection network Digital systems(DS) are pervasive in modern society. Digital computers.
Design, Synthesis and Test of Network on Chips
ATM SWITCHING. SWITCHING A Switch is a network element that transfer packet from Input port to output port. A Switch is a network element that transfer.
QoS Support in High-Speed, Wormhole Routing Networks Mario Gerla, B. Kannan, Bruce Kwan, Prasasth Palanti,Simon Walton.
High-Level Interconnect Architectures for FPGAs An investigation into network-based interconnect systems for existing and future FPGA architectures Nick.
High-Level Interconnect Architectures for FPGAs Nick Barrow-Williams.
1 Message passing architectures and routing CEG 4131 Computer Architecture III Miodrag Bolic Material for these slides is taken from the book: W. Dally,
F. Gharsalli, S. Meftali, F. Rousseau, A.A. Jerraya TIMA laboratory 46 avenue Felix Viallet Grenoble Cedex - France Embedded Memory Wrapper Generation.
Computer Networks with Internet Technology William Stallings
Department of Computer Science and Engineering The Pennsylvania State University Akbar Sharifi, Emre Kultursay, Mahmut Kandemir and Chita R. Das Addressing.
Architectural and Physical Design Optimization for Efficient Intra-Tile Communication Liza Rodriguez Aurelio Morales EEL Embedded Systems Dept.
CS 8501 Networks-on-Chip (NoCs) Lukasz Szafaryn 15 FEB 10.
Cisco 3 - Switching Perrine. J Page 16/4/2016 Chapter 4 Switches The performance of shared-medium Ethernet is affected by several factors: data frame broadcast.
University of Michigan, Ann Arbor
Run-time Adaptive on-chip Communication Scheme 林孟諭 Dept. of Electrical Engineering National Cheng Kung University Tainan, Taiwan, R.O.C.
Soc 5.1 Chapter 5 Interconnect Computer System Design System-on-Chip by M. Flynn & W. Luk Pub. Wiley 2011 (copyright 2011)
Dynamic Traffic Distribution among Hierarchy Levels in Hierarchical Networks-on-Chip Ran Manevich, Israel Cidon, and Avinoam Kolodny Group Research QNoC.
Module R R RRR R RRRRR RR R R R R Access Regulation to Hot-Modules in Wormhole NoCs Isask’har (Zigi) Walter Supervised by: Israel Cidon, Ran Ginosar and.
SCORES: A Scalable and Parametric Streams-Based Communication Architecture for Modular Reconfigurable Systems Abelardo Jara-Berrocal, Ann Gordon-Ross NSF.
Mohamed ABDELFATTAH Andrew BITAR Vaughn BETZ. 2 Module 1 Module 2 Module 3 Module 4 FPGAs are big! Design big systems High on-chip communication.
A Low-Area Interconnect Architecture for Chip Multiprocessors Zhiyi Yu and Bevan Baas VLSI Computation Lab ECE Department, UC Davis.
Univ. of TehranIntroduction to Computer Network1 An Introduction to Computer Networks University of Tehran Dept. of EE and Computer Engineering By: Dr.
System on a Programmable Chip (System on a Reprogrammable Chip)
Network-on-Chip Paradigm Erman Doğan. OUTLINE SoC Communication Basics  Bus Architecture  Pros, Cons and Alternatives NoC  Why NoC?  Components 
Lecture 23: Interconnection Networks
ESE532: System-on-a-Chip Architecture
Pablo Abad, Pablo Prieto, Valentin Puente, Jose-Angel Gregorio
Azeddien M. Sllame, Amani Hasan Abdelkader
OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel
NoC: Network OR Chip? Israel Cidon Technion.
Israel Cidon, Ran Ginosar and Avinoam Kolodny
Network-on-Chip Programmable Platform in Versal™ ACAP Architecture
Presentation transcript:

1 Evgeny Bolotin – ClubNet Nov 2003 Network on Chip (NoC) Evgeny Bolotin Supervisors: Israel Cidon, Ran Ginosar and Avinoam Kolodny ClubNet - November 2003 EE Department, Technion, Israel

2 Evgeny Bolotin – ClubNet Nov 2003 Outline Motivation – SoC Communication Current Solutions NoC Concept QNoC Arch. & Design Process QNoC Example NoC Cost Summary

3 Evgeny Bolotin – ClubNet Nov 2003 Growing Chip Density 1998 Asic  m 2003 SoC  m Memory, I/O P Design complexity - high IP reuse Efficient high performance interconnect Scalability of communication architecture

4 Evgeny Bolotin – ClubNet Nov 2003 The Growing Gap: Computation vs. Communication Taken From ITRS, 2001

5 Evgeny Bolotin – ClubNet Nov 2003 The Gap: Something to think about Taken from W.J. Dally presentation: Computer architecture is all about interconnect (it is now and it will be more so in 2010) HPCA Panel February 4, 2002

6 Evgeny Bolotin – ClubNet Nov 2003 SoC Interconnect Interconnect Dominates Delay and Power in VDSM Doesn’t Scale with Technology:  interconnect power + delay more dominant as the technology improves Globally Asynchronous Locally Synchronous (GALS ) Systems  distributed systems on single silicon substrate

7 Evgeny Bolotin – ClubNet Nov 2003 “Bus Inheritance” From Board level into Chip level… P P

8 Evgeny Bolotin – ClubNet Nov 2003 Typical Solution-Bus Shared Bus B B Segmented Bus

9 Evgeny Bolotin – ClubNet Nov 2003 Original bus features: One transaction at a time Central Arbiter Limited bandwidth Synchronous Low cost Typical Solution-Bus Multi-Level Segmented Bus B B Segmented Bus New features: Versatile bus architectures Pipelining capability Burst transfer Split transactions Transaction preemption and resume Transaction reordering… B B Is it still?

10 Evgeny Bolotin – ClubNet Nov 2003 Well-known Industry Solutions AMBA ( Advanced Microcontroller Bus Architecture) Ownership : ARM SiliconBackplane  Network Ownership : Sonics Core-Connect Ownership : IBM

11 Evgeny Bolotin – ClubNet Nov 2003 Traditional SoC Nightmare Variety of dedicated interfaces Poor separation between computation and communication. Design Complexity Unpredictable performance

12 Evgeny Bolotin – ClubNet Nov 2003 Solution – Network on Chip Networks are preferred over buses: Higher bandwidth Concurrency, effective spatial reuse of resources Higher levels of abstraction Modularity - Design Productivity Improvement Scalability

13 Evgeny Bolotin – ClubNet Nov 2003 Solution – Network on Chip Requirements: Different QoS must be supported Bandwidth Latency Distributed deadlock free routing Distributed congestion/flow control Low VLSI Cost

14 Evgeny Bolotin – ClubNet Nov 2003 NoC vs. “Off-Chip” Networks What is Different? Routers on Planar Grid Topology Short PTP Links between routers Unique VLSI Cost Sensitivity: Area-Routers and Links Power

15 Evgeny Bolotin – ClubNet Nov 2003 NoC vs. “Off-Chip Networks” No legacy protocols to be compliant with … No software  simple and hardware efficient protocols Different operating env. (no dynamic changes and failures) Custom Network Design – You design what you need! Replace Example1: Replace modules

16 Evgeny Bolotin – ClubNet Nov 2003 NoC vs. “Off-Chip Networks” Example2: Adapt Links Adapt Links Example3: Trim Unnecessary (ports, buffers, routers, links)

17 Evgeny Bolotin – ClubNet Nov 2003 QNoC: QoS NoC Define Service Levels (SLs): Signaling Real-Time Read/Write (RD/WR) Block-Transfer Different QoS for each SL

18 Evgeny Bolotin – ClubNet Nov 2003 QNoC Architecture Mesh Topology Fixed shortest path routing (X-Y) Simple Router (no tables, simple logic) Power efficient communication No deadlock scenario

19 Evgeny Bolotin – ClubNet Nov 2003 Wormhole Packet: Flit QNoC Architecture Wormhole Routing For reduced buffering Flit (routing info) Flit

20 Evgeny Bolotin – ClubNet Nov 2003 QNoC Wormhole Router

21 Evgeny Bolotin – ClubNet Nov 2003 QNoC Design Process Take full network and customize using a-priori known parameters

22 Evgeny Bolotin – ClubNet Nov 2003 QNoC Design Process - Optimization Trim Unnecessary Resources Adjust each link capacity according to its load Equal link utilization across the chip Example: (Uniform mesh)

23 Evgeny Bolotin – ClubNet Nov 2003 QNoC Design Process - Cost est. QNoC Cost : Total wire-length and FF-count Wire cost ~ wire-length Dynamic Power ~ wire-length and U Logic Cost ~ FF-count

24 Evgeny Bolotin – ClubNet Nov 2003 Design Example

25 Evgeny Bolotin – ClubNet Nov 2003 Design Example Representative Design Example, each module contains 4 traffic sources: Traffic Source Traffic interpretation Average Packet Length [flits] Average Inter-arrival time [ns] Total Load per Module ETE requirements For 99.9% of packets Signaling Every 100 cycles each module sends interrupt to a random target Mbps 20 ns (several cycles) Real-Time Periodic connection from each module: 320 voice channels of 64 Kb/s Mbps 125 μs (Voice-8 KHz frame) RD/WR Random target RD/WR transaction every ~25 cycles Gbps ~150 ns (tens of cycles) Block-Transfer Random target Block- Transfer transaction every ~ cycles Gbps 50 µs (Several tx. delays on typ. bus)

26 Evgeny Bolotin – ClubNet Nov 2003 Uniform Scenario - Observations Calculated Link Load Relations:

27 Evgeny Bolotin – ClubNet Nov 2003 Uniform Scenario - Observations Various Link BW allocations: Allocated Link BW [Gbps] Average Link Utilization [%] Packet ETE delay of packets [ns or cycles] Signaling (99.9%) Real-Time (99.9%) RD/WR (99%) Block- Transfer (99%) 2560Gbps Gbps Gbps Desired QoS

28 Evgeny Bolotin – ClubNet Nov 2003 Uniform Scenario - Observations Fixed Network Configuration -Uniform Traffic Network behavior under different traffic loads? BLOCK ETE Delay Traffic Load Real-Time RD/WR Signaling

29 Evgeny Bolotin – ClubNet Nov 2003 QNoC vs. Alternative Solutions (4x4 mesh, uniform traffic) Uniform scenario (Same QoS): Arch.FrequencyUtilization Av. Link Width QNoC 1GHz30%28 Bus 50 MHz50%3 700 PTP 100MHz80%6 BUSQNoCPTP Cost

30 Evgeny Bolotin – ClubNet Nov 2003 NoC Cost Scalability vs. Alternatives Compare the cost of: NoC Non-Segmented Bus (NS-Bus) Segmented Bus (S-Bus) Point-To-Point (PTP)

31 Evgeny Bolotin – ClubNet Nov 2003 NoC Cost Scalability vs. Alternatives

32 Evgeny Bolotin – ClubNet Nov 2003 Summary Why NoC? What is Different in NoC QNoC NoC is Best